📄 def21262.h
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// Timer Registers
#define TMSTAT (0x1400) // GP Timer Status Register
//TMxSTAT all address the same register (TMSTAT)
#define TM0STAT (0x1400) // GP Timer 0 Status register
#define TM0CTL (0x1401) // GP Timer 0 Control register
#define TM0CNT (0x1402) // GP Timer 0 Count register
#define TM0PRD (0x1403) // GP Timer 0 Period register
#define TM0W (0x1404) // GP Timer 0 Width register
#define TM1STAT (0x1408) // GP Timer 1 Status register
#define TM1CTL (0x1409) // GP Timer 1 Control register
#define TM1CNT (0x140a) // GP Timer 1 Count register
#define TM1PRD (0x140b) // GP Timer 1 Period register
#define TM1W (0x140c) // GP Timer 1 Width register
#define TM2STAT (0x1410) // GP Timer 2 Status register
#define TM2CTL (0x1411) // GP Timer 2 Control register
#define TM2CNT (0x1412) // GP Timer 2 Count register
#define TM2PRD (0x1413) // GP Timer 2 Period register
#define TM2W (0x1414) // GP Timer 2 Width register
// POWER MGT Registers
#define PMCTL (0x2000) // Power management control register
// DAI Registers
// DMA Parameter Registers
#define IDP_DMA_I0 (0x2400) // IDP DMA Channel 0 Index Register
#define IDP_DMA_I1 (0x2401) // IDP DMA Channel 1 Index Register
#define IDP_DMA_I2 (0x2402) // IDP DMA Channel 2 Index Register
#define IDP_DMA_I3 (0x2403) // IDP DMA Channel 3 Index Register
#define IDP_DMA_I4 (0x2404) // IDP DMA Channel 4 Index Register
#define IDP_DMA_I5 (0x2405) // IDP DMA Channel 5 Index Register
#define IDP_DMA_I6 (0x2406) // IDP DMA Channel 6 Index Register
#define IDP_DMA_I7 (0x2407) // IDP DMA Channel 7 Index Register
#define IDP_DMA_M0 (0x2410) // IDP DMA Channel 0 Modify Register
#define IDP_DMA_M1 (0x2411) // IDP DMA Channel 1 Modify Register
#define IDP_DMA_M2 (0x2412) // IDP DMA Channel 2 Modify Register
#define IDP_DMA_M3 (0x2413) // IDP DMA Channel 3 Modify Register
#define IDP_DMA_M4 (0x2414) // IDP DMA Channel 4 Modify Register
#define IDP_DMA_M5 (0x2415) // IDP DMA Channel 5 Modify Register
#define IDP_DMA_M6 (0x2416) // IDP DMA Channel 6 Modify Register
#define IDP_DMA_M7 (0x2417) // IDP DMA Channel 7 Modify Register
#define IDP_DMA_C0 (0x2420) // IDP DMA Channel 0 Count Register
#define IDP_DMA_C1 (0x2421) // IDP DMA Channel 1 Count Register
#define IDP_DMA_C2 (0x2422) // IDP DMA Channel 2 Count Register
#define IDP_DMA_C3 (0x2423) // IDP DMA Channel 3 Count Register
#define IDP_DMA_C4 (0x2424) // IDP DMA Channel 4 Count Register
#define IDP_DMA_C5 (0x2425) // IDP DMA Channel 5 Count Register
#define IDP_DMA_C6 (0x2426) // IDP DMA Channel 6 Count Register
#define IDP_DMA_C7 (0x2427) // IDP DMA Channel 7 Count Register
// SRU Registers
#define SRU_CLK0 (0x2430) // SRU Clock Control Register 0
#define SRU_CLK1 (0x2432) // SRU Clock Control Register 1
#define SRU_CLK2 (0x2433) // SRU Clock Control Register 2
#define SRU_CLK3 (0x2434) // SRU Clock Control Register 3
#define SRU_DAT0 (0x2440) // SRU Data Control Register 0
#define SRU_DAT1 (0x2441) // SRU Data Control Register 1
#define SRU_DAT2 (0x2442) // SRU Data Control Register 2
#define SRU_DAT3 (0x2444) // SRU Data Control Register 3
#define SRU_DAT4 (0x2445) // SRU Data Control Register 4
#define SRU_FS0 (0x2450) // SRU FS Control Register 0
#define SRU_FS1 (0x2452) // SRU FS Control Register 1
#define SRU_FS2 (0x2453) // SRU FS Control Register 2
#define SRU_PIN0 (0x2460) // SRU Pin Control Register 0
#define SRU_PIN1 (0x2461) // SRU Pin Control Register 1
#define SRU_PIN2 (0x2462) // SRU Pin Control Register 2
#define SRU_PIN3 (0x2463) // SRU Pin Control Register 3
#define SRU_EXT_MISCA (0x2470) // SRU External Misc. A Control Register
#define SRU_EXT_MISCB (0x2471) // SRU External Misc. B Control Register
#define SRU_PBEN0 (0x2478) // SRU Pin Enable Register 0
#define SRU_PBEN1 (0x2479) // SRU Pin Enable Register 1
#define SRU_PBEN2 (0x247A) // SRU Pin Enable Register 2
#define SRU_PBEN3 (0x247B) // SRU Pin Enable Register 3
#define DAI_PIN_PULLUP (0x247D) // Controls whether DAI bin buffers have pullups enabled
#define DAI_IRPTL_FE (0x2480) // DAI Falling Edge Interrupt Latch Register
#define DAI_IRPTL_RE (0x2481) // DAI Rising Edge Interrupt Latch Register
#define DAI_IRPTL_PRI (0x2484) // DAI Interrupt Priority Register
#define DAI_IRPTL_H (0x2488) // DAI High Priority Interrupt Latch Register
#define DAI_IRPTL_L (0x2489) // DAI Low Priority Interrupt Latch Register
#define IDP_CTL (0x24B0) // IDP Control Register
#define IDP_PP_CTL (0x24B1) // IDP Parallel Port Control Register
#define DAI_STAT (0x24B8) // DAI Status Register
#define DAI_PIN_STAT (0x24B9) // DAI Pin Buffer Status Register
#define PCG_CTLA_0 (0x24C0) // Precision Clock A Control Register 0
#define PCG_CTLA_1 (0x24C1) // Precision Clock A Control Register 1
#define PCG_CTLB_0 (0x24C2) // Precision Clock B Control Register 0
#define PCG_CTLB_1 (0x24C3) // Precision Clock B Control Register 1
#define PCG_PW (0x24C4) // Precision Clock Pulse Width Control Register
#define IDP_FIFO (0x24D0) // IDP FIFO packing mode register
//========================================================================----
// System Register bit definitions
//========================================================================----
// MODE1 and MMASK registers
#define BR8 (BIT_0) // Bit 0: Bit-reverse for I8
#define BR0 (BIT_1) // Bit 1: Bit-reverse for I0 (uses DMS0- only )
#define SRCU (BIT_2) // Bit 2: Alt. register select for comp. units
#define SRD1H (BIT_3) // Bit 3: DAG1 alt. register select (7-4)
#define SRD1L (BIT_4) // Bit 4: DAG1 alt. register select (3-0)
#define SRD2H (BIT_5) // Bit 5: DAG2 alt. register select (15-12)
#define SRD2L (BIT_6) // Bit 6: DAG2 alt. register select (11-8)
#define SRRFH (BIT_7) // Bit 7: Register file alt. select for R(15-8)
#define SRRFL (BIT_10) // Bit 10: Register file alt. select for R(7-0)
#define NESTM (BIT_11) // Bit 11: Interrupt nesting enable
#define IRPTEN (BIT_12) // Bit 12: Global interrupt enable
#define ALUSAT (BIT_13) // Bit 13: Enable ALU fixed-pt. saturation
#define SSE (BIT_14) // Bit 14: Enable short word sign extension
#define TRUNCATE (BIT_15) // Bit 15: 1=fltg-pt. truncation 0=Rnd to nearest
#define RND32 (BIT_16) // Bit 16: 1=32-bit fltg-pt.rounding 0=40-bit rnd
#define CSEL (BIT_17|BIT_18) // Bit 17-18: CSelect: Bus Mastership
#define PEYEN (BIT_21) // Bit 21: Processing Element Y enable
#define SIMD (BIT_21) // Bit 21: Enable SIMD Mode
#define BDCST9 (BIT_22) // Bit 22: Load Broadcast for I9
#define BDCST1 (BIT_23) // Bit 23: Load Broadcast for I1
#define CBUFEN (BIT_24) // Bit 23: Circular Buffer Enable
// MODE2 register
#define IRQ0E (BIT_0) // Bit 0: IRQ0- 1=edge sens. 0=level sens.
#define IRQ1E (BIT_1) // Bit 1: IRQ1- 1=edge sens. 0=level sens.
#define IRQ2E (BIT_2) // Bit 2: IRQ2- 1=edge sens. 0=level sens.
#define CADIS (BIT_4) // Bit 4: Cache disable
#define TIMEN (BIT_5) // Bit 5: Timer enable
#define BUSLK (BIT_6) // Bit 6: External bus lock
#define CAFRZ (BIT_19) // Bit 19: Cache freeze
#define IIRAE (BIT_20) // Bit 20: Illegal IOP Register Access Enable
#define U64MAE (BIT_21) // Bit 21: Unaligned 64-bit Memory Access Enable
// ASTATx and ASTATy registers
#ifdef SUPPORT_DEPRECATED_USAGE
// Several of these (AV, AC, MV, SV, SZ) are assembler-reserved keywords,
so this style is now deprecated. If these are defined, the assembler-
reserved keywords are still available in lowercase, e.g.,
IF sz JUMP LABEL1.
# define AZ (BIT_0) // Bit 0: ALU result zero or fltg-pt. underflow
# define AV (BIT_1) // Bit 1: ALU overflow
# define AN (BIT_2) // Bit 2: ALU result negative
# define AC (BIT_3) // Bit 3: ALU fixed-pt. carry
# define AS (BIT_4) // Bit 4: ALU X input sign (ABS and MANT ops)
# define AI (BIT_5) // Bit 5: ALU fltg-pt. invalid operation
# define MN (BIT_6) // Bit 6: Multiplier result negative
# define MV (BIT_7) // Bit 7: Multiplier overflow
# define MU (BIT_8) // Bit 8: Multiplier fltg-pt. underflow
# define MI (BIT_9) // Bit 9: Multiplier fltg-pt. invalid operation
# define AF (BIT_10) // Bit 10: ALU fltg-pt. operation
# define SV (BIT_11) // Bit 11: Shifter overflow
# define SZ (BIT_12) // Bit 12: Shifter result zero
# define SS (BIT_13) // Bit 13: Shifter input sign
# define BTF (BIT_18) // Bit 18: Bit test flag for system registers
# define CACC0 (BIT_24) // Bit 24: Compare Accumulation Bit 0
# define CACC1 (BIT_25) // Bit 25: Compare Accumulation Bit 1
# define CACC2 (BIT_26) // Bit 26: Compare Accumulation Bit 2
# define CACC3 (BIT_27) // Bit 27: Compare Accumulation Bit 3
# define CACC4 (BIT_28) // Bit 28: Compare Accumulation Bit 4
# define CACC5 (BIT_29) // Bit 29: Compare Accumulation Bit 5
# define CACC6 (BIT_30) // Bit 30: Compare Accumulation Bit 6
# define CACC7 (BIT_31) // Bit 31: Compare Accumulation Bit 7
#endif
#define ASTAT_AZ (BIT_0) // Bit 0: ALU result zero or fltg-pt. u'flow
#define ASTAT_AV (BIT_1) // Bit 1: ALU overflow
#define ASTAT_AN (BIT_2) // Bit 2: ALU result negative
#define ASTAT_AC (BIT_3) // Bit 3: ALU fixed-pt. carry
#define ASTAT_AS (BIT_4) // Bit 4: ALU X input sign(ABS and MANT ops)
#define ASTAT_AI (BIT_5) // Bit 5: ALU fltg-pt. invalid operation
#define ASTAT_MN (BIT_6) // Bit 6: Multiplier result negative
#define ASTAT_MV (BIT_7) // Bit 7: Multiplier overflow
#define ASTAT_MU (BIT_8) // Bit 8: Multiplier fltg-pt. underflow
#define ASTAT_MI (BIT_9) // Bit 9: Multiplier fltg-pt. invalid op.
#define ASTAT_AF (BIT_10) // Bit 10: ALU fltg-pt. operation
#define ASTAT_SV (BIT_11) // Bit 11: Shifter overflow
#define ASTAT_SZ (BIT_12) // Bit 12: Shifter result zero
#define ASTAT_SS (BIT_13) // Bit 13: Shifter input sign
#define ASTAT_BTF (BIT_18) // Bit 18: Bit test flag for system registers
#define ASTAT_CACC0 (BIT_24) // Bit 24: Compare Accumulation Bit 0
#define ASTAT_CACC1 (BIT_25) // Bit 25: Compare Accumulation Bit 1
#define ASTAT_CACC2 (BIT_26) // Bit 26: Compare Accumulation Bit 2
#define ASTAT_CACC3 (BIT_27) // Bit 27: Compare Accumulation Bit 3
#define ASTAT_CACC4 (BIT_28) // Bit 28: Compare Accumulation Bit 4
#define ASTAT_CACC5 (BIT_29) // Bit 29: Compare Accumulation Bit 5
#define ASTAT_CACC6 (BIT_30) // Bit 30: Compare Accumulation Bit 6
#define ASTAT_CACC7 (BIT_31) // Bit 31: Compare Accumulation Bit 7
// STKYx and STKYy registers
// bits 0 to 9 in both STKYx and STKYY, bits 17 to 26 in STKYx only
#define AUS (BIT_0) // Bit 0: ALU fltg-pt. underflow
#define AVS (BIT_1) // Bit 1: ALU fltg-pt. overflow
#define AOS (BIT_2) // Bit 2: ALU fixed-pt. overflow
#define AIS (BIT_5) // Bit 5: ALU fltg-pt. invalid operation
#define MOS (BIT_6) // Bit 6: Multiplier fixed-pt. overflow
#define MVS (BIT_7) // Bit 7: Multiplier fltg-pt. overflow
#define MUS (BIT_8) // Bit 8: Multiplier fltg-pt. underflow
#define MIS (BIT_9) // Bit 9: Multiplier fltg-pt. invalid operation
// STKYx register *ONLY*
#define CB7S (BIT_17) // Bit 17: DAG1 circular buffer 7 overflow
#define CB15S (BIT_18) // Bit 18: DAG2 circular buffer 15 overflow
#define IIRA (BIT_19) // Bit 19: Illegal IOP Register Access
#define U64MA (BIT_20) // Bit 20: Unaligned 64-bit Memory Access
#define PCFL (BIT_21) // Bit 21: PC stack full
#define PCEM (BIT_22) // Bit 22: PC stack empty
#define SSOV (BIT_23) // Bit 23: Status stack overflow (MODE1 and ASTAT)
#define SSEM (BIT_24) // Bit 24: Status stack empty
#define LSOV (BIT_25) // Bit 25: Loop stack overflow
#define LSEM (BIT_26) // Bit 26: Loop stack empty
// IRPTL and IMASK and IMASKP registers
#define EMUI (BIT_0) // Bit 0 - Emulator Interrupt
#define RSTI (BIT_1) // Bit 1 - Reset
#define IICDI (BIT_2) // Bit 2 - Illegal Input Condition Detected
#define SOVFI (BIT_3) // Bit 3 - Stack overflow
#define TMZHI (BIT_4) // Bit 4 - Timer = 0 (high priority)
#define BKPI (BIT_6) // Bit 6 - Hardware Breakpoint interrupt
#define IRQ2I (BIT_8) // Bit 8 - IRQ2- asserted
#define IRQ1I (BIT_9) // Bit 9 - IRQ1- asserted
#define IRQ0I (BIT_10) // Bit 10 - IRQ0- asserted
#define DAIHI (BIT_11) // Bit 11 - DAI interrupt
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