📄 def21262.h
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#define BIT_13 0x00002000
#define BIT_14 0x00004000
#define BIT_15 0x00008000
#define BIT_16 0x00010000
#define BIT_17 0x00020000
#define BIT_18 0x00040000
#define BIT_19 0x00080000
#define BIT_20 0x00100000
#define BIT_21 0x00200000
#define BIT_22 0x00400000
#define BIT_23 0x00800000
#define BIT_24 0x01000000
#define BIT_25 0x02000000
#define BIT_26 0x04000000
#define BIT_27 0x08000000
#define BIT_28 0x10000000
#define BIT_29 0x20000000
#define BIT_30 0x40000000
#define BIT_31 0x80000000
//=====================================================================
// A macro to use these in C
#define REG(ADDRESS) *(volatile int *) ADDRESS
//==============================================================================
//
// I/O Processor Register Address Memory Map
//
//==============================================================================
// Emulation/Breakpoint Registers
#define EEMUIN (0x30020) // Emulator Input FIFO
#define EEMUSTAT (0x30021) // Enhanced Emulation Status Register
#define EEMUOUT (0x30022) // Emulator Output FIFO
#define OSPID (0x30023) // Operating System Process ID
#define SYSCTL (0x30024) // System Control Register
#define BRKCTL (0x30025) // Hardware Breakpoint Control Register
#define REVPID (0x30026) // Emulation/Revision ID Register
#define PSA1S (0x300a0) // Instruction Breakpoint Address Start #1
#define PSA1E (0x300a1) // Instruction Breakpoint Address End #1
#define PSA2S (0x300a2) // Instruction Breakpoint Address Start #2
#define PSA2E (0x300a3) // Instruction Breakpoint Address End #2
#define PSA3S (0x300a4) // Instruction Breakpoint Address Start #3
#define PSA3E (0x300a5) // Instruction Breakpoint Address End #3
#define PSA4S (0x300a6) // Instruction Breakpoint Address Start #4
#define PSA4E (0x300a7) // Instruction Breakpoint Address End #4
#define DMA1S (0x300b2) // Data Memory Breakpoint Address Start #1
#define DMA1E (0x300b3) // Data Memory Breakpoint Address Start #1
#define DMA2S (0x300b4) // Data Memory Breakpoint Address Start #2
#define DMA2E (0x300b5) // Data Memory Breakpoint Address Start #2
#define D1IC (0x300b6)
#define D1ID (0x300b7)
#define PMDAS (0x300b8) // Program Memory Breakpoint Address Start #1
#define PMDAE (0x300b9) // Program Memory Breakpoint Address Start #1
#define D2IC (0x300bc)
#define D2ID (0x300bd)
#define EMUN (0x300ae) // Number of Breakpoints before EMU interrupt
#define IOAS (0x300b0) // I/O Breakpoint Address Start #1
#define IOAE (0x300b1) // I/O Breakpoint Address Start #1
// Serial Port registers (SP01)
#define SPCTL0 (0xc00) // SPORT 0 control register
#define SPCTL1 (0xc01) // SPORT 1 control register
#define DIV0 (0xc02) // SPORT 0 divisor for transmit/receive SCLK0 and FS0
#define DIV1 (0xc03) // SPORT 1 divisor for transmit/receive SCLK1 and FS1
#define SPMCTL01 (0xc04) // SPORTs 0 & 1 Multichannel Control Register
#define MT0CS0 (0xc05) // SPORT 0 multichannel tx select, channels 31 - 0
#define MT0CS1 (0xc06) // SPORT 0 multichannel tx select, channels 63 - 32
#define MT0CS2 (0xc07) // SPORT 0 multichannel tx select, channels 95 - 64
#define MT0CS3 (0xc08) // SPORT 0 multichannel tx select, channels 127 - 96
#define MR1CS0 (0xc09) // SPORT 1 multichannel rx select, channels 31 - 0
#define MR1CS1 (0xc0A) // SPORT 1 multichannel rx select, channels 63 - 32
#define MR1CS2 (0xc0B) // SPORT 1 multichannel rx select, channels 95 - 64
#define MR1CS3 (0xc0C) // SPORT 1 multichannel rx select, channels 127 - 96
#define MT0CCS0 (0xc0D) // SPORT 0 multichannel tx compand select, channels 31 - 0
#define MT0CCS1 (0xc0E) // SPORT 0 multichannel tx compand select, channels 63 - 32
#define MT0CCS2 (0xc0F) // SPORT 0 multichannel tx compand select, channels 95 - 64
#define MT0CCS3 (0xc10) // SPORT 0 multichannel tx compand select, channels 127 - 96
#define MR1CCS0 (0xc11) // SPORT 1 multichannel rx compand select, channels 31 - 0
#define MR1CCS1 (0xc12) // SPORT 1 multichannel rx compand select, channels 63 - 32
#define MR1CCS2 (0xc13) // SPORT 1 multichannel rx compand select, channels 95 - 64
#define MR1CCS3 (0xc14) // SPORT 1 multichannel rx compand select, channels 127 - 96
#define SPCNT0 (0xc15) // SPORT Count register - status information for internal clock and fs
#define SPCNT1 (0xc16) // SPORT Count register - status information for internal clock and fs
#define IISP0A (0xc40) // Internal memory DMA address
#define IMSP0A (0xc41) // Internal memory DMA access modifier
#define CSP0A (0xc42) // Contains number of DMA transfers remaining
#define CPSP0A (0xc43) // Points to next DMA parameters
#define IISP0B (0xc44) // Internal memory DMA address
#define IMSP0B (0xc45) // Internal memory DMA access modifier
#define CSP0B (0xc46) // Contains number of DMA transfers remaining
#define CPSP0B (0xc47) // Points to next DMA parameters
#define IISP1A (0xc48) // Internal memory DMA address
#define IMSP1A (0xc49) // Internal memory DMA access modifier
#define CSP1A (0xc4A) // Contains number of DMA transfers remaining
#define CPSP1A (0xc4B) // Points to next DMA parameters
#define IISP1B (0xc4C) // Internal memory DMA address
#define IMSP1B (0xc4D) // Internal memory DMA access modifier
#define CSP1B (0xc4E) // Contains number of DMA transfers remaining
#define CPSP1B (0xc4F) // Points to next DMA parameters
#define TXSP0A (0xc60) // SPORT 0A transmit data register
#define RXSP0A (0xc61) // SPORT 0A receive data register
#define TXSP0B (0xc62) // SPORT 0B transmit data register
#define RXSP0B (0xc63) // SPORT 0B receive data register
#define TXSP1A (0xc64) // SPORT 1A transmit data register
#define RXSP1A (0xc65) // SPORT 1A receive data register
#define TXSP1B (0xc66) // SPORT 1B transmit data register
#define RXSP1B (0xc67) // SPORT 1B receive data register
// Serial Port registers (SP23)
#define SPCTL2 (0x400) // SPORT 2 control register
#define SPCTL3 (0x401) // SPORT 3 control register
#define DIV2 (0x402) // SPORT 2 divisor for transmit/receive SCLK2 and FS2
#define DIV3 (0x403) // SPORT 3 divisor for transmit/receive SCLK3 and FS3
#define SPMCTL23 (0x404) // SPORTs 2 & 3 Multichannel Control Register
#define MT2CS0 (0x405) // SPORT 2 multichannel tx select, channels 31 - 0
#define MT2CS1 (0x406) // SPORT 2 multichannel tx select, channels 63 - 32
#define MT2CS2 (0x407) // SPORT 2 multichannel tx select, channels 95 - 64
#define MT2CS3 (0x408) // SPORT 2 multichannel tx select, channels 127 - 96
#define MR3CS0 (0x409) // SPORT 3 multichannel rx select, channels 31 - 0
#define MR3CS1 (0x40A) // SPORT 3 multichannel rx select, channels 63 - 32
#define MR3CS2 (0x40B) // SPORT 3 multichannel rx select, channels 95 - 64
#define MR3CS3 (0x40C) // SPORT 3 multichannel rx select, channels 127 - 96
#define MT2CCS0 (0x40D) // SPORT 2 multichannel tx compand select, channels 31 - 0
#define MT2CCS1 (0x40E) // SPORT 2 multichannel tx compand select, channels 63 - 32
#define MT2CCS2 (0x40F) // SPORT 2 multichannel tx compand select, channels 95 - 64
#define MT2CCS3 (0x410) // SPORT 2 multichannel tx compand select, channels 127 - 96
#define MR3CCS0 (0x411) // SPORT 3 multichannel rx compand select, channels 31 - 0
#define MR3CCS1 (0x412) // SPORT 3 multichannel rx compand select, channels 63 - 32
#define MR3CCS2 (0x413) // SPORT 3 multichannel rx compand select, channels 95 - 64
#define MR3CCS3 (0x414) // SPORT 3 multichannel rx compand select, channels 127 - 96
#define SPCNT2 (0x416) // SPORT Count register - status information for internal clock and fs
#define IISP2A (0x440) // Internal memory DMA address
#define IMSP2A (0x441) // Internal memory DMA access modifier
#define CSP2A (0x442) // Contains number of DMA transfers remaining
#define CPSP2A (0x443) // Points to next DMA parameters
#define IISP2B (0x444) // Internal memory DMA address
#define IMSP2B (0x445) // Internal memory DMA access modifier
#define CSP2B (0x446) // Contains number of DMA transfers remaining
#define CPSP2B (0x447) // Points to next DMA parameters
#define IISP3A (0x448) // Internal memory DMA address
#define IMSP3A (0x449) // Internal memory DMA access modifier
#define CSP3A (0x44A) // Contains number of DMA transfers remaining
#define CPSP3A (0x44B) // Points to next DMA parameters
#define IISP3B (0x44C) // Internal memory DMA address
#define IMSP3B (0x44D) // Internal memory DMA access modifier
#define CSP3B (0x44E) // Contains number of DMA transfers remaining
#define CPSP3B (0x44F) // Points to next DMA parameters
#define TXSP2A (0x460) // SPORT 2A transmit data register
#define RXSP2A (0x461) // SPORT 2A receive data register
#define TXSP2B (0x462) // SPORT 2B transmit data register
#define RXSP2B (0x463) // SPORT 2B receive data register
#define TXSP3A (0x464) // SPORT 3A transmit data register
#define RXSP3A (0x465) // SPORT 3A receive data register
#define TXSP3B (0x466) // SPORT 3B transmit data register
#define RXSP3B (0x467) // SPORT 3B receive data register
// Serial Port registers (SP3)
#define SPCTL4 (0x800) // SPORT 4 control register
#define SPCTL5 (0x801) // SPORT 5 control register
#define DIV4 (0x802) // SPORT 4 divisor for transmit/receive SCLK4 and FS4
#define DIV5 (0x803) // SPORT 5 divisor for transmit/receive SCLK5 and FS5
#define SPMCTL45 (0x804) // SPORTs 4 & 5 Multichannel Control Register
#define MT4CS0 (0x805) // SPORT 4 multichannel tx select, channels 31 - 0
#define MT4CS1 (0x806) // SPORT 4 multichannel tx select, channels 63 - 32
#define MT4CS2 (0x807) // SPORT 4 multichannel tx select, channels 95 - 64
#define MT4CS3 (0x808) // SPORT 4 multichannel tx select, channels 127 - 96
#define MR5CS0 (0x809) // SPORT 5 multichannel rx select, channels 31 - 0
#define MR5CS1 (0x80A) // SPORT 5 multichannel rx select, channels 63 - 32
#define MR5CS2 (0x80B) // SPORT 5 multichannel rx select, channels 95 - 64
#define MR5CS3 (0x80C) // SPORT 5 multichannel rx select, channels 127 - 96
#define MT4CCS0 (0x80D) // SPORT 4 multichannel tx compand select, channels 31 - 0
#define MT4CCS1 (0x80E) // SPORT 4 multichannel tx compand select, channels 63 - 32
#define MT4CCS2 (0x80F) // SPORT 4 multichannel tx compand select, channels 95 - 64
#define MT4CCS3 (0x810) // SPORT 4 multichannel tx compand select, channels 127 - 96
#define MR5CCS0 (0x811) // SPORT 5 multichannel rx compand select, channels 31 - 0
#define MR5CCS1 (0x812) // SPORT 5 multichannel rx compand select, channels 63 - 32
#define MR5CCS2 (0x813) // SPORT 5 multichannel rx compand select, channels 95 - 64
#define MR5CCS3 (0x814) // SPORT 5 multichannel rx compand select, channels 127 - 96
#define SPCNT3 (0x816) // SPORT Count register - status information for internal clock and fs
#define IISP4A (0x840) // Internal memory DMA address
#define IMSP4A (0x841) // Internal memory DMA access modifier
#define CSP4A (0x842) // Contains number of DMA transfers remaining
#define CPSP4A (0x843) // Points to next DMA parameters
#define IISP4B (0x844) // Internal memory DMA address
#define IMSP4B (0x845) // Internal memory DMA access modifier
#define CSP4B (0x846) // Contains number of DMA transfers remaining
#define CPSP4B (0x847) // Points to next DMA parameters
#define IISP5A (0x848) // Internal memory DMA address
#define IMSP5A (0x849) // Internal memory DMA access modifier
#define CSP5A (0x84A) // Contains number of DMA transfers remaining
#define CPSP5A (0x84B) // Points to next DMA parameters
#define IISP5B (0x84C) // Internal memory DMA address
#define IMSP5B (0x84D) // Internal memory DMA access modifier
#define CSP5B (0x84E) // Contains number of DMA transfers remaining
#define CPSP5B (0x84F) // Points to next DMA parameters
#define TXSP4A (0x860) // SPORT 4A transmit data register
#define RXSP4A (0x861) // SPORT 4A receive data register
#define TXSP4B (0x862) // SPORT 4B transmit data register
#define RXSP4B (0x863) // SPORT 4B receive data register
#define TXSP5A (0x864) // SPORT 5A transmit data register
#define RXSP5A (0x865) // SPORT 5A receive data register
#define TXSP5B (0x866) // SPORT 5B transmit data register
#define RXSP5B (0x867) // SPORT 5B receive data register
// SPI Registers
#define SPICTL (0x1000) // SPI Control Register
#define SPIFLG (0x1001) // SPI Flag register
#define SPISTAT (0x1002) // SPI Status register
#define TXSPI (0x1003) // SPI transmit data register
#define RXSPI (0x1004) // SPI receive data register
#define SPIBAUD (0x1005) // SPI baud setup register
#define RXSPI_SHADOW (0x1006) // SPI receive data shadow register
#define IISPI (0x1080) // Internal memory DMA address
#define IMSPI (0x1081) // Internal memory DMA access modifier
#define CSPI (0x1082) // Contains number of DMA transfers remaining
#define CPSPI (0x1083) // Points to next DMA parameters
#define SPIDMAC (0x1084) // SPI DMA control register
// Parallel port registers
#define PPCTL (0x1800) // Parallel port control register
#define TXPP (0x1808) // Parallel port transmit data register
#define RXPP (0x1809) // Parallel port receive data register
#define EIPP (0x1810) // External memory DMA address
#define EMPP (0x1811) // External memory DMA access modifier
#define ECPP (0x1812) // Contains number of external DMA accesses remaining
#define IIPP (0x1818) // Internal memory DMA address
#define IMPP (0x1819) // Internal memory DMA access modifier
#define ICPP (0x181a) // Contains number of DMA transfers remaining
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