def21262.h

在ADSP-2126x上编写的优化过的IIR滤波器程序（用c和汇编编写）。

/*=============================================================================

    def21266.h  (c) Copyright 2003 Analog Devices, Inc.  All rights reserved.

    SYSTEM & IOP REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-21266
    This include file contains a list of macro "defines" to enable the
    programmer to use symbolic names for the following ADSP-21266 facilities:
     - instruction condition codes
     - system register bit definitions
     - IOP register address memory map
     - *most* IOP control/status register bit definitions

    Here are some example uses:

        bit set mode1 BR0|IRPTEN|ALUSAT;
        ustat1=BSO|HPM01|HMSWF;
        DM(SYSCTL)=ustat1;

------------------------------------------------------------------------------

    3.DEC.2002 - BM - Created
    8.DEC.2002 - MW - renamed PPCTL bits so 1 indicates true
                        PPDIR   ->PPTRAN    (transfer direction)
                        PPHC    ->PPBHC     (bus hold cycle)
                        PPEW    ->PP16      (external bus width, 0=8,1=16)

   13.DEC.2002 - MW - New comments and for SPIFLG register
                    - replaced C comment style w/ C++ style: "//"
                    - renamed SPIDCTL register -> SPIDMAC
                    - renamed SPIFLG bits
                        SPIDS   -> ISSS     (input service-select status)
                        FLSx    -> DSxEN    (SPI Device select enable)
                        SPIFLGx -> SPIDSx   (SPI Device Select control)

                    - renamed SPICTL bits
                        DF      -> MSBF     (most significant byte first)
                        ESPIDS  -> ISSEN    (input slave select enable)
                        TXBUFCLR-> TXFLSH   (Flush the transmit buffer)
                        RXBUFCLR-> RXFLSH   (Flush the receive buffer)
                        CK      -> CLKPL    (clock polarity)

                    - renamed PMCFG bits to remove misconception of N indicating 'Numerator'
                        PLLNEN  ->DIVEN    (pll divider enable)
                        PLLNx   ->PLLDx     (divide by 2,4,8, or 16)

    16.DEC.2002 - MW - Renamed SYSCTL bits:
                        FLG02IRQ0 ->IRQ0EN
                        FLG12IRQ1 ->IRQ1EN
                        FLG22IRQ1 ->IRQ2EN
                        FLG32TMXP ->TMREXPEN

                     - renamed SPIDMAC bits:
                        SPIDIR  -> SPIRCV
                        FIFOCLEAR -> FIFOFLSH
                        EINTEN  -> INTERR
                        CINTEN  -> INTEN
                        DRBSY   -> SPIOVF
                        DTXE    -> SPIUNF

    07.JAN.2003 - JT - Renamed IRPTL/IMASK/IMASKP bits:
                        SPR0I   -> SP1I
                        SPR1I   -> SP3I
                        SPR2I   -> SP5I

                     - Renamed LIRPTL bits:
                        SPT0I   -> SP0I
                        SPT1I   -> SP2I
                        SPT2I   -> SP4I
                        SPT0IMSK -> SP0IMSK
                        SPT1IMSK -> SP2IMSK
                        SPT2IMSK -> SP4IMSK
                        SPT0IMSKP -> SP0IMSKP
                        SPT1IMSKP -> SP2IMSKP
                        SPT2IMSKP -> SP4IMSKP

    21.JAN.2003 - MW - Removed MISR register definitions (only used during testing)

    23.JAN.2003 - MW - IRQ3 is reserved in SHARC-EX, removed all references

    03.MAR.2003 - MW - SPISTAT register updated (TX and RX buffers each have
                       just one bit to indicate status.)
                        RXS1,RXS0 -> RXS
                        TXS1,TXS0 -> TXS

    05.MAR.2003 - BM - Added DAI Register Definitions
                        Note: Group (A-F) field names do not match the spec
                        b/c of conflicts between names.
                        Default is _O where possible.
                        Groups A-C & F all named with _O (OUTPUT)
                        Group D named with _P (PIN)
                        Group E named with _M (MISC)


    12.MAR.2003 - BM - Added Parentheses to or'ed bits to make C-compliant
        old definition - Bit_1|Bit_2
        new definition - (Bit_1|Bit_2)

    13.MAR.2003 - BM - In PPCTL: PPES -> PPBS

    14.MAR.2003 - BM - Instituted naming convention for DMA parameter
                    registers and transfer registers (All peripherals conform)

                    All DMA parameter registers (II, IM, C, IC, EI, EM, EC):
                        IIxx -> IISPxx (Serial Port)
                        IISX -> IISPI (SPI)
                        PPII -> IIPP (Parallel Port)

                    All transfer registers:
                        TXxx -> TXSPxx (Serial Port)
                        RXxx -> RXSPxx

                        SPITX -> TXSPI (SPI)
                        SPIRX -> RXSPI

                        PPTX -> TXPP (Parallel Port)
                        PPRX -> RXPP

    17.MAR.2003 - BM -  Added TXCOL to SPISTAT
                        Changed SP22TMR -> SP23TMR

    18.MAR.2003 - BM -  Changes in SPCTL
                            DDIR -> SPTRAN
                            SENDN -> LSBF

    07.APR.2003 - BM -  Fixed IMSPI typo.

    08.APR.2003 - BM -  SPxyMCTL -> SPMCTLxy
                        In SPISTAT
                            TXE -> TUNF
                            RBSY -> ROVF

    10.APR.2003 - BM -  Removed erroneous PMCTL bits

    14.APR.2003 - MW -  Renamed PP-Waitstates PP-Duration since they specify the
                        number of core-clock cycles per PP Data-Cycle. (comments
                        added below)

                        In PPCTL
                            PPWSn -> PPDURn+1 (eg. WS3->PPDUR4, WS8->PPDUR9,etc)

    07.MAY.2003 - BM - Removed erroneous SYSCTL bits
                       Added explanation for DAI Group naming (See 05.MAR.2003)

    16.MAY.2003 - MW - commented out {{ #define WL8 0x0 //SPI Word Length = 8 }}
                       because people will be inclined to "bit set WL8" which
                       would incorrectly set bit zero.

    19.MAY.2003 - BM - Added Generic TMSTAT definition.
                       Changed TMxOVF -> TIMxOVF

    21.MAY.2003 - BM - Updated Example in header to reflect correct registers

    23.MAY.2003 - MW - Renamed SPIFLAG bits:
                            SPIDSn -> SPIFLGn

    23.MAY.2003 - BM - Added descriptions to Emulator Registers and bit
                        definitions for EEMUSTAT and BRKCTL

    27.MAY.2003 - BM - Changed all LJ CLOCK to Precision Clock
                       Opcode conflict: Bit 15 of MODE1 TRUNC -> TRUNCATE

    06.JUN.2003 - BM - SPIRX_SHADOW -> RXSPI_SHADOW

    11.JUN.2003 - MW - in Precision Clock Pulse Width Control Register (PCG_PW)
                        PWFSA (0x0000FFFC) -> PWFSA (0x0000FFFF)
                        PWFSB (0xFFFC0000) -> PWFSB (0xFFFF0000)

                     - renamed INT_MISC* -> INV_MISC*

    13.JUN.2003 - MW - Overhauled SRU-routing register/bit def's and comments

                    o Added defs to support following SRU-routing model which
                      requires the (location:length) of each bitfield. (This
                      example selects the input for SPORT0 Clock to be the
                      output of DAI Pin Buffer 18.)

                     R0=DM(SRU_CLK0);
                     R1=DAI_PB18_O;
                     R0=R0 or FDEP R1 by SPORT0_CLK_I;
                     dm(SRU_CLK0)=R0;

                    o Added missing definition of DAI_PIN_PULLUP (0x247D)
                    o Renamed DAI-Pin related fields to DAI Pin Buffer
                          DAI_Pxx -> DAI_PBxx
                          DAI_PINENxx -> DAI_PBENxx
                    o Appended routing-group letter to output signal defs,
                      for example:  SPORT5_CLK_O -> SPORT5_CLK_Oa
                                     SPORT0_DA_O  -> SPORT0_DA_Ob
                                     SPORT5_FS_O  -> SPORT5_FS_Oc
                      (note: DAI_PBxx_O sources do not require this change)

    23.JUN.2003 - MW - Deleted _BITS definitions
                     - Changed _I definitions to use start:length as follows

                     (BIT_5|BIT_6|BIT_9|BIT_10|BIT_11) -> 5:5
                     (BIT_0|BIT_1|BIT_2|BIT_3|BIT_4|BIT_5) -> 0:6
                       etc...

    11.JULY.2003 - MW - Removed SRU bit field definitions and moved them to SRU.h

    23.JULY.2003 - BM - Updated IDP_PDAP definitions to avoid ambiguity

    30.JULY.2003 - BM - Corrected TIMxEN and TIMxDIS definitions.

    10.SEPT.2003 - BM - Added REG() Macro for accessing memory mapped registers.

    20.OCT.2003  - BM - Corrected guard #ifdef position to first non-comment
                        Defined WL8 in SPICTL again. This will not cause problems.
                        (See 16.MAY.2003 comment)

=============================================================================*/

//==================================================================
// ADSP-2126x definitions
#ifndef __DEF2126x_H_
#define __DEF2126x_H_

#define BIT_0 0x00000001
#define BIT_1 0x00000002
#define BIT_2 0x00000004
#define BIT_3 0x00000008
#define BIT_4 0x00000010
#define BIT_5 0x00000020
#define BIT_6 0x00000040
#define BIT_7 0x00000080
#define BIT_8 0x00000100
#define BIT_9 0x00000200
#define BIT_10 0x00000400
#define BIT_11 0x00000800
#define BIT_12 0x00001000