pmgrxsc1.s

针对Intel Xscale PXA255的WinCE boot loader源代码包！极具参考价值！

; For preliminary module testing with no actual suspend / resume, uncomment the TEST_STUB_PWR_OFF definition below.
;
;      TITLE("XSC1 Firmware Initialization")
;++
;
; Copyright (c) 1999, 2002  Intel Corporation
;
; $Modtime: $
;--

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;;   NOTES
;;
;; Mini-data cache not supported by Windows* CE yet, so not handled here.
;;
;;   End NOTES
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


    OPT     2                               ; disable listing

    INCLUDE kxarm.h
    INCLUDE XSC1.inc
    INCLUDE XSC1BD.inc
    INCLUDE fwXsc1.inc
    INCLUDE sa11x1.inc

    IF PLAT_LUBBOCK = "1"
    INCLUDE lubbock.mac
    ENDIF

    IF :DEF: USING_COPROCSUPPORT
    IMPORT XSC1SetCP0Acc
    IMPORT XSC1GetCP0Acc
    ENDIF    ;Endif of USING_COPROCSUPPORT

    IMPORT FlushDCache
    IMPORT OEMInitDebugSerialKernel    
    IMPORT InitDebugEther
    IMPORT test
    
    ;OPT     128                            ; disable listing of macro expansions
    OPT     1                               ; reenable listing

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;
;   Debug and development optional assembly switches

    
;TEST_STUB_PWR_OFF       EQU 1               ; Before real content
;TEST_SHOW_LEDS          EQU 1
;TEST_WAKE_SKIP_GP0      EQU 1
;TEST_WAKE_SKIP_RTC      EQU 1
;TEST_SHOW_CKSM          EQU 1
;TEST_SHOW_CKEN          EQU 1

;TEST_FORCING_GPIO1_WAKEUP       EQU 1
;TEST_LED_DISPLAY         
;TEST_LED_DISPLAY_FORCE_SHORT    EQU 1
;TEST_INCLUDE_THIS_ANYWAY       EQU 1
;TEST_NOT_REALLY_SLEEPING    EQU 1

REAL_RESTORING_CP0_AND_14    EQU 1

REAL_NOT_ONLY_REG_SAVE_RSTR    EQU 1

  IF :DEF: REAL_NOT_ONLY_REG_SAVE_RSTR
    ; Don't define any of these if just testing register save / restore

;TEST_CLEARING_RTC_INTS         EQU 1
REAL_RESTORING_GPIOS           EQU 1
REAL_RESTORING_OST    EQU 1

REAL_RESTORING_ICMR    EQU 1
  IF :DEF: REAL_RESTORING_ICMR
TEST_MASK_OFF_ALL_ICMR         EQU 1
  ENDIF; :DEF: REAL_RESTORING_ICMR

REAL_RESTORING_FPGA            EQU 1
  IF :DEF: REAL_RESTORING_FPGA
    ; Don't shut it down unless you're going to restore it!
TEST_SHUTTING_DOWN_FPGA     EQU 1
  ENDIF; :DEF: REAL_RESTORING_FPGA

  ENDIF; :DEF: REAL_NOT_ONLY_REG_SAVE_RSTR

REAL_FLUSH_DATA_CACHE    EQU 1


;;  Local definitions.  Should move to xsc1.inc and maybe follow a new naming convention.

; Register bit definitions
RTC_AL              EQU 0x00000001 
RTC_HZ              EQU 0x00000002

PWER_GPIO_BITS      EQU 0x0000FFFF  ; GPIOs 0..15 are possible wakeup sources.

                                        ; Pin positions 81..95 are reserved.
GPIOREG2_RESERVED_AND_MASK  EQU 0x0001FFFF  ;  and must be set to 0.
                                       ; For the GAFRs, the reserved bits are
GAFR2_H_RESERVED_AND_MASK   EQU 0x00000003  ;  GAFR2_H (only two not reserved)

; PCFR definitions
   IF PLAT_RTECH = "1"
PMGR_PCFR_VAL     EQU   PCFR_OPDE:OR:PCFR_FP:OR:PCFR_FS  ; When sleeping: Disable 32MHz osc, force PCMCIA and nCS lines
   ELSE
PMGR_PCFR_VAL     EQU   PCFR_OPDE  ; When sleeping: Disable 32MHz osc, force PCMCIA and nCS lines
   ENDIF ; //PLAT_RTECH

; PWER definitions
PMGR_PWER_WERTC EQU  0x80000000 ; Bit 31, enables RTC wakeup


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Interesting PGSRn definitions in platform context


;; GPIO lines to be forced high (memory chip selects and PCMCIA negative enables):
;; All others forced low to save power

;nCS[1..5] are static chip selects under the control of the PGSR.
;nCS[0] is the boot memory chip select.  It is not under PGSR control.
;No other memory chip selects are under the control of the PGSR.
;

   IF PLAT_RTECH = "1"
;nSDCS (SDRAAM chip selects) and nCSx
;
; Bit definitions for PGSRs: same as GPIOs, actually.

;   PGSR0: 0 .. 31
PGSR_nCFBusOn  	EQU 0x00010000  ; pin 16: bit 16
PGSR_nAudio33  	EQU 0x00020000  ; pin 17: bit 17

;   PGSR1  32 .. 63
PGSR_nDTR       EQU 0x00000100  ; pin 40: bit 8
PGSR_nRTS       EQU 0x00000200  ; pin 41: bit 9
PGSR_ButtCom    EQU 0x04000000  ; pin 58: bit 26
PGSR_AMPOFF     EQU 0x80000000  ; pin 63: bit 31

;   PGSR2 64 .. 80
PGSR_nCFPwrOn   EQU 0x00001000  ; pin 76: bit 12

;   All others cleared in PGSRs.


    ; In XSC1BD, all nCSx are either actually or potentially connected and
    ;   so should be set high (deselecting target devices) during sleep.
    ; Also disable all controllable PCMCIA lines (active low)

PMGR_PGSR0_SET_MASK EQU (PGSR_nCFBusOn:OR:PGSR_nAudio33)
;PMGR_PGSR1_SET_MASK EQU (PGSR_nDTR:OR:PGSR_nRTS:OR:PGSR_ButtCom:OR:PGSR_AMPOFF)
PMGR_PGSR1_SET_MASK EQU (PGSR_AMPOFF:OR:PGSR_ButtCom)
PMGR_PGSR2_SET_MASK EQU (PGSR_nCFPwrOn)

   ELSE
;nSDCS (SDRAAM chip selects) and nCSx
;
; Bit definitions for PGSRs: same as GPIOs, actually.

;   PGSR0: 0 .. 31
PGSR_nCS1       EQU 0x00008000  ; pin 15: bit 15

;   PGSR1  32 .. 63
PGSR_nCS5       EQU 0x00000002  ; pin 33: bit 1
PGSR_nDTR       EQU 0x00000100  ; pin 40: bit 8
PGSR_nRTS       EQU 0x00000200  ; pin 41: bit 9


PGSR_nPOE       EQU 0x00010000  ; pin 48: bit 16
PGSR_nPWE       EQU 0x00020000  ; pin 49: bit 17
PGSR_nPIOR      EQU 0x00040000  ; pin 50: bit 18
PGSR_nPIOW      EQU 0x00080000  ; pin 51: bit 19
PGSR_nPCE1      EQU 0x00100000  ; pin 52: bit 20
PGSR_nPCE2      EQU 0x00200000  ; pin 53 bit  21
PGSR_nP_MASK    EQU 0x003F0000  ; all PCMCIA-GPIO bits

;   PGSR2 64 .. 80
PGSR_nCS2       EQU 0x00004000  ; pin 78: bit 14
PGSR_nCS3       EQU 0x00008000  ; pin 79: bit 15
PGSR_nCS4       EQU 0x00010000  ; pin 80: bit 16

;   All others cleared in PGSRs.


;    IF PLAT_LUBBOCK = "1"
    ; In XSC1BD, all nCSx are either actually or potentially connected and
    ;   so should be set high (deselecting target devices) during sleep.
    ; Also disable all controllable PCMCIA lines (active low)

PMGR_PGSR0_SET_MASK EQU (PGSR_nCS1)
PMGR_PGSR1_SET_MASK EQU (PGSR_nCS5:OR:PGSR_nDTR:OR:PGSR_nRTS:OR:PGSR_nP_MASK)
PMGR_PGSR2_SET_MASK EQU (PGSR_nCS2:OR:PGSR_nCS3:OR:PGSR_nCS4)
;    ENDIF

    IF PLAT_SANDGATE = "1"
; @@@ TBD
;   PMGR_PGSR0_SET_MASK EQU (PGSR_nCS1)
;   PMGR_PGSR1_SET_MASK EQU (PGSR_nCS5)
;   PMGR_PGSR2_SET_MASK EQU (PGSR_nCS2:OR:PGSR_nCS3:OR:PGSR_nCS4)

    ENDIF
   ENDIF ; // PLAT_RTECH
;
;PCFR:  FS AND FP ARE SET TO ZERO, MEANING FORCED TO PGSR VALUE, NOT FLOATED
;        DS = 0    (No Deep Sleep)
;        OPDE = 1 (Stop 3 MHz oscillator during sleep):  Assume RTC driven off 32K osc.
;

;; Set wakeup  conditions.
    IF PLAT_LUBBOCK = "1"
    ; In XSC1BD, wake up only for GPIO1 (S12) or GPIO0 (S13 or UCB1400 touch interrupt)
    ;   For this platform, GPIO 0 is falling edge triggered, 1 is rising edge triggered. 

    ; Rising edge wakeup triggers
  
   IF PLAT_RTECH = "1"
PMGR_PRER_BITS  EQU  0x0000 ; DCD
   ELSE   
PMGR_PRER_BITS  EQU  0x0002 ; GPIO 1 wakes on rising edge
   ENDIF ; PLAT_RTECH
;;; End.   
    ; Falling edge wakeup triggers

  
   IF PLAT_RTECH = "1"
PMGR_PFER_BITS  EQU  0x000D ; GPIO 0, #DCD and nCD wake on falling edge
   ELSE
    IF :DEF: TEST_WAKE_SKIP_GP0
PMGR_PFER_BITS  EQU  0x0000 ; Skip GPIO 0 wakes on falling edge
    ELSE ; TEST_WAKE_SKIP_GP0
PMGR_PFER_BITS  EQU  0x0001 ; GPIO 0 wakes on falling edge
    ENDIF ; TEST_WAKE_SKIP_GP0
   ENDIF ; PLAT_RTECH

    ENDIF ; PLAT_LUBBOCK


    IF PLAT_SANDGATE = "1"

    ; Rising edge wakeup triggers
PMGR_PRER_BITS  EQU  0x0002 ; GPIO 1 wakes on rising edge

    ; Falling edge wakeup triggers
PMGR_PFER_BITS  EQU  0x0000 ; Not using any falling edge triggers

    ENDIF; PLAT_SANDGATE
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;;;;;;;;;;;;;;
;;
;;  Some hex display macros
;;

;; 
;;   Note: restricted to this macro because MS ARM assembler
;;      can't deal with the ldr r0, =($parameter) construct in
;;      a macro definition.
;; 

;;    R1 is undefined

    MACRO
    VIRT_HEX_DISP_REG_NOT_R1  $dispReg, $delay

    IF :DEF: PLAT_LUBBOCK
    IF :DEF: TEST_LED_DISPLAY

        ldr     r1,  =(FPGA_REGS_BASE_U_VIRTUAL)
        str     $dispReg,  [r1, #HEXLED_OFFSET]
    IF :DEF: TEST_LED_DISPLAY_FORCE_SHORT
        mov     r1, #0x10
    ELSE
        ldr     r1, =($delay)
    ENDIF ; TEST_LED_DISPLAY_FORCE_SHORT
11
        subs    r1, r1, #1
        bne     %B11

    ENDIF; :DEF: TEST_LED_DISPLAY
    ENDIF; :DEF: PLAT_LUBBOCK

    MEND

;; End of macro defs
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    TEXTAREA


;
; XSC1GetSPSR - Returns the Saved Program Status Register
;
; This routine is called byby the IRQ interrupt handler when
; PMU is active and capturing data
;
;       Entry   Interrupts disabled
;       Exit    Interrupts disabled
;       Uses    r0 returns SPSR

    LEAF_ENTRY XSC1GetSPSR

    mrs     r0, SPSR
      IF Interworking :LOR: Thumbing
         bx  lr
      ELSE
         mov  pc, lr          ; return
      ENDIF

;; End of XSC1GetSPSR()
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;
; CPUEnterIdle - system idle
;
; NOTE: Implementation of OEMIdle moved to OEMIdle.c
;
; This routine is called by OEMIdle in order to enter IDLE mode
;
;
;       Entry   Interrupts disabled
;       Exit    none
;       Uses    r0
;

    LEAF_ENTRY CPUEnterIdle

    ldr     r0, =0x01                       ; 1 = Idle Mode 
    mcr     p14, 0, r0, c7, c0, 0           ; Enter Idle mode
      IF Interworking :LOR: Thumbing
         bx  lr
      ELSE
         mov  pc, lr          ; return
      ENDIF

;; End of CPUEnterIdle()
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;;;;;;;;;;;;;;;;;;;;;;;;;
;;  PwrMgrGetSleepDataCksm subroutine

    LEAF_ENTRY PwrMgrGetSleepDataCksm
;  Virtual addressing assumed.  (Can't use in pre-MMU startup without a change)
;  chksum returns in R0
;  Also uses R1,2,3
;  Assumes return address in link register

    ; do Checksum on the Sleepdata

;    ldr r0, =(0x44440011)
    VIRT_HEX_DISP_REG_NOT_R1  r0, 0x100  ; just a marker

    ldr     r3, =(SLEEPDATA_BASE_U_VIRTUAL)             ; get pointer to SLEEPDATA
    ldr     r0, =(0x5A72)                     ; Pick a non-zero seed.
                                            ; get size of data structure (in words)
    ldr     r2, =(SLEEPDATA_SIZE-1)         ; but skip checksum record.
30
    ldr     r1, [r3], #4
    add     r0, r0, r1
    mov     r0, r0, ROR #31
    subs    r2, r2, #1
    bne     %b30

    IF Interworking :LOR: Thumbing
        bx  lr
    ELSE
        mov  pc, lr          ; return
    ENDIF

;; End of PwrMgrGetSleepDataCksm()
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;;
;; Go to sleeeep, my ba-a-by...
;;  This is a really long lullaby.
;;

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    END