📄 cpregxsc1.s
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;
; Copyright (c) Microsoft Corporation. All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
; TITLE("XSC1 CoRegister Access Routines")
;++
;
; Copyright (c) 2001 Intel Corporation
;
;--
; Conditional Includes
IF PLAT_LUBBOCK = "1"
INCLUDE Lubbock.mac
ENDIF
OPT 2 ; disable listing
INCLUDE kxarm.h
INCLUDE XSC1.inc
INCLUDE XSC1BD.inc ; explicit inclusion required for Sandgate
INCLUDE fwXsc1.inc
OPT 1 ; reenable listing
TEXTAREA
;
; ReadPMUReg - Read the PMU Register
;
; This routine reads the designated PMU register via CoProcesser 14.
;
; Uses r0 - arg1 - PMU register number to read (0-3)
; r0 - integer result - value read in register
;
;
LEAF_ENTRY ReadPMUReg
cmp r0, #3
bhi RRet
cmp r0, #0
bne RReg1
mrc p14, 0, r0, c0, c0, 0
b RRet
RReg1
cmp r0, #1
bne RReg2
mrc p14, 0, r0, c1, c0, 0
b RRet
RReg2
cmp r0, #2
bne RReg3
mrc p14, 0, r0, c2, c0, 0
b RRet
RReg3
cmp r0, #3
bne RRet
mrc p14, 0, r0, c3, c0, 0
RRet
IF Interworking :LOR: Thumbing
bx lr
ELSE
mov pc, lr ; return
ENDIF
;
; WritePMUReg - Writes to the PMU Register
;
; This routine writes to the designated PMU register via CoProcesser 14.
;
; Uses
; r0 - arg1 - PMU register number to write (0-3)
; r1 - arg2 - Value to write to PMU register
;
LEAF_ENTRY WritePMUReg
stmfd sp!, {r1}
cmp r0, #3
bhi WRet
cmp r0, #0
bne WReg1
mcr p14, 0, r1, c0, c0, 0
b WRet
WReg1
cmp r0, #1
bne WReg2
mcr p14, 0, r1, c1, c0, 0
b WRet
WReg2
cmp r0, #2
bne WReg3
mcr p14, 0, r1, c2, c0, 0
b WRet
WReg3
cmp r0, #3
bne WRet
mcr p14, 0, r1, c3, c0, 0
WRet
ldmfd sp!, {r1}
IF Interworking :LOR: Thumbing
bx lr
ELSE
mov pc, lr ; return
ENDIF
;
; XSC1EnterTurbo - Enters Turbo Mode
;
; Uses r0 - contains value for writing to PWRMODE coprocessor register
;
LEAF_ENTRY XSC1EnterTurbo
ldr r0, =0x01 ; PWRMODE (c6) = 1 to
mcr p14, 0, r0, c6, c0, 0 ; enter Turbo mode
IF Interworking :LOR: Thumbing
bx lr
ELSE
mov pc, lr ; return
ENDIF
;
; XSC1ExitTurbo - Exits Turbo Mode
;
; Uses r0 - contains value for writing to PWRMODE coprocessor register
;
LEAF_ENTRY XSC1ExitTurbo
ldr r0, =0x0 ; PWRMODE (c6) = 0 to
mcr p14, 0, r0, c6, c0, 0 ; exit Turbo mode
IF Interworking :LOR: Thumbing
bx lr
ELSE
mov pc, lr ; return
ENDIF
;
;XSC1ReadTurbo - Reads CCLKCFG to see if we're in Turbo Mode
;
; Uses r0 - contains return value: 1 if in Turbo, 0 otherwise
; r1 - results of CCLKCFG
;
LEAF_ENTRY XSC1ReadTurbo
stmfd sp!, {r1}
mrc p14, 0, r1, c6, c0, 0 ; Read CCLKCFG
ands r0, r1, #0x01
ldmfd sp!, {r1}
IF Interworking :LOR: Thumbing
bx lr
ELSE
mov pc, lr ; return
ENDIF
;
; XSC1GetCPUId - Get the CPU ID from CP15 R0 Register
;
; This routine reads R0 from CoProcesser 15 to get the CPU ID
;
; Uses r0 - return value of CPU ID
;
LEAF_ENTRY XSC1GetCPUId
mrc p15, 0, r0, c0, c0, 0
IF Interworking :LOR: Thumbing
bx lr
ELSE
mov pc, lr ; return
ENDIF
LEAF_ENTRY XSC1FreqChange
;
; XSC1FreqChange - Do a Frequency Change
;
; Uses
; r0 - arg1 - Value for Turbo Mode
; 0 = no turbo
; 1 = turbo
;
stmfd sp!, {r1-r3}
cmp r0, #1
bgt FreqRet
orr r0, r0, #2 ; set FCS=1
;
; for B0 bug, need to do a "store" before freq change.
;
ldr r1, =MEMC_BASE_U_VIRTUAL
ldr r2, [r1, #MDREFR_OFFSET]
; write back mdrefr
;
str r2, [r1, #MDREFR_OFFSET]
mcr p14, 0, r0, c6, c0, 0 ; do Freq Change
FreqRet
ldmfd sp!, {r1-r3}
IF Interworking :LOR: Thumbing
bx lr
ELSE
mov pc, lr ; return
ENDIF
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
LEAF_ENTRY TURN_ON_BTB
; Turn on the BTB via cp15.1[11]
;
;... IF :DEF: A1_Cotulla
ldr r0, =DRIVER_GLOBALS_CPU_ID_LOCATION ; Start of driver globals misc section
ldr r1,[r0] ; Grab the CPU ID from the stored location
ldr r2, =COTULLA_CP15_A1_VAL
cmp r1, r2
bne NOT_A1_COTULLA
IF Interworking :LOR: Thumbing
bx lr
ENDIF
NOT_A1_COTULLA
;... ENDIF
mcr p15, 0, r0, c7, c5, 0 ; flush the icache & BTB
mrc p15,0,r0,c1,c0,0
orr r0, r0, #0x800
mcr p15,0,r0,c1,c0,0
IF Interworking :LOR: Thumbing
bx lr
ELSE
mov pc, lr ; return
ENDIF
IF :DEF: USING_COPROCSUPPORT
;
; XSC1GetCP0Acc - Get the Accumulator Register from CP0
;
; This routine reads R0 from CoProcesser 0
;
; Uses r0, - R0 contains a pointer to the alloced memory buffer of 8 bytes long
;
LEAF_ENTRY XSC1GetCP0Acc
stmdb sp!, {r0 - r4} ; stmfd
mov r4, r0 ;Save R0 to R4, so pointer value doesn't get killed by CPWAIT
mrc p15, 0, r3, c15, c0, 0 ;Get Reg15 of CP15 for Access to CP0
mov r2, #0x1 ;Load R2 with mask for setting lowest bit
orr r1, r3, r2 ;OR current value with 1 to set the lowest bit
mcr p15, 0, r1, c15, c0, 0 ;Now set the value back into R15 of CP15
CPWAIT
IF WINCEOSVER = "300"
DCD 0xec521000 ;Perform Mra - Need to be hardcoded for lack of ARMV4 Compiler support
ELSE
mra r1, r2, acc0 ;R1 & R2 now contain Accumulator 0
ENDIF
CPWAIT
stmia r4!, {r1-r2} ; Store R1 & R2 into the memory location pointed to by R4
mcr p15, 0, r3, c15, c0, 0 ;Now set the value back into R15 of CP15
CPWAIT
ldmia sp!, {r0 - r4}
IF Interworking :LOR: Thumbing
bx lr
ELSE
mov pc, lr ; return
ENDIF
;
; XSC1SetCP0Acc - Set CP0's Accumulator Register
;
; This routine sets R0 on CoProcessor 0
;
; Uses r0 - pointer to the memory buffer containing the 40-bit value
; Uses r1, r2 - R1 & R2 contain the value to be written to the Accumulator Register
; r1 = bits 0:31, r2 = 32:39
;
LEAF_ENTRY XSC1SetCP0Acc
stmdb sp!, {r0 - r4} ; stmfd
mov r4, r0 ;Save R0 to R4, so pointer value doesn't get killed by CPWAIT
mrc p15, 0, r3, c15, c0, 0 ;Get Reg15 of CP15 for Access to CP0
mov r2, #0x1 ;Load R2 with mask for setting lowest bit
orr r1, r3, r2 ;OR current value with 1 to set the lowest bit
mcr p15, 0, r1, c15, c0, 0 ;Now set the value back into R15 of CP15
CPWAIT
ldmia r4!, {r1-r2} ; Load R1 & R2 from the pointer in R4
IF WINCEOSVER = "300"
DCD 0xec421000 ;Perform mar instruction - again, hardcoded for ARMV4 architecture processors
ELSE
mar acc0, r1, r2 ;Accumulator now contains R1 & R2
ENDIF
CPWAIT
mcr p15, 0, r3, c15, c0, 0 ;Now set the value back into R15 of CP15
CPWAIT
ldmia sp!, {r0 - r4}
IF Interworking :LOR: Thumbing
bx lr
ELSE
mov pc, lr ; return
ENDIF
ENDIF ;Endif of USING_COPROCSUPPORT
;
; GetCP1Regs - Gets all the registers of CP1
;
; This routine Reads all the registers of CP1
;
LEAF_ENTRY GetCP1Regs
cmp r0, #0 ; Compare R0 to make sure it's not NULL
beq %FT10 ; done
mrc p1, 0, r2, c0, c0, 0 ;Get Reg0 of Cp1
str r2, [r0], #4
mrc p1, 0, r2, c1, c0, 0 ;Get Reg1 of Cp1
str r2, [r0], #4
mrc p1, 0, r2, c2, c0, 0 ;Get Reg2 of Cp1
str r2, [r0], #4
mrc p1, 0, r2, c3, c0, 0 ;Get Reg3 of Cp1
str r2, [r0], #4
mrc p1, 0, r2, c4, c0, 0 ;Get Reg4 of Cp1
str r2, [r0], #4
mrc p1, 0, r2, c5, c0, 0 ;Get Reg5 of Cp1
str r2, [r0], #4
mrc p1, 0, r2, c6, c0, 0 ;Get Reg6 of Cp1
str r2, [r0], #4
mrc p1, 0, r2, c7, c0, 0 ;Get Reg7 of Cp1
str r2, [r0], #4
mrc p1, 0, r2, c8, c0, 0 ;Get Reg8 of Cp1
str r2, [r0], #4
mrc p1, 0, r2, c9, c0, 0 ;Get Reg9 of Cp1
str r2, [r0], #4
mrc p1, 0, r2, c10, c0, 0 ;Get Reg10 of Cp1
str r2, [r0], #4
mrc p1, 0, r2, c11, c0, 0 ;Get Reg11 of Cp1
str r2, [r0], #4
mrc p1, 0, r2, c12, c0, 0 ;Get Reg12 of Cp1
str r2, [r0], #4
mrc p1, 0, r2, c13, c0, 0 ;Get Reg13 of Cp1
str r2, [r0], #4
mrc p1, 0, r2, c14, c0, 0 ;Get Reg14 of Cp1
str r2, [r0], #4
mrc p1, 0, r2, c15, c0, 0 ;Get Reg15 of Cp1
str r2, [r0], #4
10
IF Interworking :LOR: Thumbing
bx lr
ELSE
mov pc, lr ; return
ENDIF
;
; GetCP2Regs - Gets all the registers of CP2
;
; This routine Reads all the registers of CP2
;
LEAF_ENTRY GetCP2Regs
cmp r0, #0 ; Compare R0 to make sure it's not NULL
beq %FT10 ; done
mrc p2, 0, r2, c0, c0, 0 ;Get Reg0 of Cp2
str r2, [r0], #4
mrc p2, 0, r2, c1, c0, 0 ;Get Reg1 of Cp2
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