📄 asm_init.s
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bl .sio_bw
addi r4, r0, SIO_PCSCI /* select PCSCIR */
addi r5, r0, 0x02
bl .sio_bw
addi r4, r0, SIO_PCSCD /* select PCSCDR */
addi r5, r0, 0x40
bl .sio_bw
/*
* CS1
*/
addi r4, r0, SIO_PCSCI /* select PCSCIR */
addi r5, r0, 0x05
bl .sio_bw
addi r4, r0, SIO_PCSCD /* select PCSCDR */
addi r5, r0, 0x00
bl .sio_bw
addi r4, r0, SIO_PCSCI /* select PCSCIR */
addi r5, r0, 0x05
bl .sio_bw
addi r4, r0, SIO_PCSCD /* select PCSCDR */
addi r5, r0, 0x70
bl .sio_bw
addi r4, r0, SIO_PCSCI /* select PCSCIR */
addi r5, r0, 0x06
bl .sio_bw
addi r4, r0, SIO_PCSCD /* select PCSCDR */
addi r5, r0, 0x1C
bl .sio_bw
/*
* CS2
*/
addi r4, r0, SIO_PCSCI /* select PCSCIR */
addi r5, r0, 0x08
bl .sio_bw
addi r4, r0, SIO_PCSCD /* select PCSCDR */
addi r5, r0, 0x00
bl .sio_bw
addi r4, r0, SIO_PCSCI /* select PCSCIR */
addi r5, r0, 0x09
bl .sio_bw
addi r4, r0, SIO_PCSCD /* select PCSCDR */
addi r5, r0, 0x71
bl .sio_bw
addi r4, r0, SIO_PCSCI /* select PCSCIR */
addi r5, r0, 0x0A
bl .sio_bw
addi r4, r0, SIO_PCSCD /* select PCSCDR */
addi r5, r0, 0x1C
bl .sio_bw
mtspr 8, r7 /* restore link register */
bclr 20, 0 /* return to caller */
/*
* this function writes a register to the SIO chip
*/
.sio_bw:
stb r4, 0(r3) /* write index register with register offset */
eieio
sync
stb r5, 1(r3) /* 1st write */
eieio
sync
stb r5, 1(r3) /* 2nd write */
eieio
sync
bclr 20, 0 /* return to caller */
/*
* this function reads a register from the SIO chip
*/
.sio_br:
stb r4, 0(r3) /* write index register with register offset */
eieio
sync
lbz r3, 1(r3) /* retrieve specified reg offset contents */
eieio
sync
bclr 20, 0 /* return to caller */
/*
* Print a message to COM1 in polling mode
* r10=COM1 port, r3=(char*)string
*/
.globl Printf
Printf:
lis r10, CFG_ISA_IO@h /* COM1 port */
ori r10, r10, 0x03f8
WaitChr:
lbz r0, 5(r10) /* read link status */
eieio
andi. r0, r0, 0x40 /* mask transmitter empty bit */
beq cr0, WaitChr /* wait till empty */
lbzx r0, r0, r3 /* get char */
stb r0, 0(r10) /* write to transmit reg */
eieio
addi r3, r3, 1 /* next char */
lbzx r0, r0, r3 /* get char */
cmpwi cr1, r0, 0 /* end of string ? */
bne cr1, WaitChr
blr
/*
* Print 8/4/2 digits hex value to COM1 in polling mode
* r10=COM1 port, r3=val
*/
OutHex2:
li r9, 4 /* shift reg for 2 digits */
b OHstart
OutHex4:
li r9, 12 /* shift reg for 4 digits */
b OHstart
.globl OutHex
OutHex:
li r9, 28 /* shift reg for 8 digits */
OHstart:
lis r10, CFG_ISA_IO@h /* COM1 port */
ori r10, r10, 0x03f8
OutDig:
lbz r0, 5(r10) /* read link status */
eieio
andi. r0, r0, 0x40 /* mask transmitter empty bit */
beq cr0, OutDig
sraw r0, r3, r9
clrlwi r0, r0, 28
cmpwi cr1, r0, 9
ble cr1, digIsNum
addic r0, r0, 55
b nextDig
digIsNum:
addic r0, r0, 48
nextDig:
stb r0, 0(r10) /* write to transmit reg */
eieio
addic. r9, r9, -4
bge OutDig
blr
/*
* Print 3 digits hdec value to COM1 in polling mode
* r10=COM1 port, r3=val, r7=x00, r8=x0, r9=x, r0, r6=scratch
*/
.globl OutDec
OutDec:
li r6, 10
divwu r0, r3, r6 /* r0 = r3 / 10, r9 = r3 mod 10 */
mullw r10, r0, r6
subf r9, r10, r3
mr r3, r0
divwu r0, r3, r6 /* r0 = r3 / 10, r8 = r3 mod 10 */
mullw r10, r0, r6
subf r8, r10, r3
mr r3, r0
divwu r0, r3, r6 /* r0 = r3 / 10, r7 = r3 mod 10 */
mullw r10, r0, r6
subf r7, r10, r3
lis r10, CFG_ISA_IO@h /* COM1 port */
ori r10, r10, 0x03f8
or. r7, r7, r7
bne noblank1
li r3, 0x20
b OutDec4
noblank1:
addi r3, r7, 48 /* convert to ASCII */
OutDec4:
lbz r0, 0(r13) /* slow down dummy read */
lbz r0, 5(r10) /* read link status */
eieio
andi. r0, r0, 0x40 /* mask transmitter empty bit */
beq cr0, OutDec4
stb r3, 0(r10) /* x00 to transmit */
eieio
or. r7, r7, r8
beq OutDec5
addi r3, r8, 48 /* convert to ASCII */
OutDec5:
lbz r0, 0(r13) /* slow down dummy read */
lbz r0, 5(r10) /* read link status */
eieio
andi. r0, r0, 0x40 /* mask transmitter empty bit */
beq cr0, OutDec5
stb r3, 0(r10) /* x0 to transmit */
eieio
addi r3, r9, 48 /* convert to ASCII */
OutDec6:
lbz r0, 0(r13) /* slow down dummy read */
lbz r0, 5(r10) /* read link status */
eieio
andi. r0, r0, 0x40 /* mask transmitter empty bit */
beq cr0, OutDec6
stb r3, 0(r10) /* x to transmit */
eieio
blr
/*
* Print a char to COM1 in polling mode
* r10=COM1 port, r3=char
*/
.globl OutChr
OutChr:
lis r10, CFG_ISA_IO@h /* COM1 port */
ori r10, r10, 0x03f8
OutChr1:
lbz r0, 5(r10) /* read link status */
eieio
andi. r0, r0, 0x40 /* mask transmitter empty bit */
beq cr0, OutChr1 /* wait till empty */
stb r3, 0(r10) /* write to transmit reg */
eieio
blr
/*
* Input: r3 adr to read
* Output: r3 val or -1 for error
*/
spdRead:
mfspr r26, 8 /* save link register */
lis r30, CFG_ISA_IO@h
ori r30, r30, 0x220 /* GPIO Port 1 */
li r7, 0x00
li r8, 0x100
and. r5, r3, r8
beq spdbank0
li r12, 0x08
li r4, 0x10
li r6, 0x18
b spdRead1
spdbank0:
li r12, 0x20 /* set I2C data */
li r4, 0x40 /* set I2C clock */
li r6, 0x60 /* set I2C clock and data */
spdRead1:
li r8, 0x80
bl spdStart /* access I2C bus as master */
li r10, 0xa0 /* write to SPD */
bl spdWriteByte
bl spdReadAck /* ACK returns in r10 */
cmpw cr0, r10, r7
bne AckErr /* r10 must be 0, if ACK received */
mr r10, r3 /* adr to read */
bl spdWriteByte
bl spdReadAck
cmpw cr0, r10, r7
bne AckErr
bl spdStart
li r10, 0xa1 /* read from SPD */
bl spdWriteByte
bl spdReadAck
cmpw cr0, r10, r7
bne AckErr
bl spdReadByte /* return val in r10 */
bl spdWriteAck
bl spdStop /* release I2C bus */
mr r3, r10
mtspr 8, r26 /* restore link register */
blr
/*
* ACK error occurred
*/
AckErr:
bl spdStop
orc r3, r0, r0 /* return -1 */
mtspr 8, r26 /* restore link register */
blr
/*
* Routines to read from RAM spd.
* r30 - GPIO Port1 address in all cases.
* r4 - clock mask for SPD
* r6 - port mask for SPD
* r12 - data mask for SPD
*/
waitSpd:
li r0, 0x1000
mtctr r0
wSpd:
bdnz wSpd
bclr 20, 0 /* return to caller */
/*
* establish START condition on I2C bus
*/
spdStart:
mfspr r27, 8 /* save link register */
stb r6, 0(r30) /* set SDA and SCL */
eieio
stb r6, 1(r30) /* switch GPIO to output */
eieio
bl waitSpd
stb r4, 0(r30) /* reset SDA */
eieio
bl waitSpd
stb r7, 0(r30) /* reset SCL */
eieio
bl waitSpd
mtspr 8, r27
bclr 20, 0 /* return to caller */
/*
* establish STOP condition on I2C bus
*/
spdStop:
mfspr r27, 8 /* save link register */
stb r7, 0(r30) /* reset SCL and SDA */
eieio
stb r6, 1(r30) /* switch GPIO to output */
eieio
bl waitSpd
stb r4, 0(r30) /* set SCL */
eieio
bl waitSpd
stb r6, 0(r30) /* set SDA and SCL */
eieio
bl waitSpd
stb r7, 1(r30) /* switch GPIO to input */
eieio
mtspr 8, r27
bclr 20, 0 /* return to caller */
spdReadByte:
mfspr r27, 8
stb r4, 1(r30) /* set GPIO for SCL output */
eieio
li r9, 0x08
li r10, 0x00
loopRB:
stb r7, 0(r30) /* reset SDA and SCL */
eieio
bl waitSpd
stb r4, 0(r30) /* set SCL */
eieio
bl waitSpd
lbz r5, 0(r30) /* read from GPIO Port1 */
rlwinm r10, r10, 1, 0, 31
and. r5, r5, r12
beq clearBit
ori r10, r10, 0x01 /* append _1_ */
clearBit:
stb r7, 0(r30) /* reset SCL */
eieio
bl waitSpd
addic. r9, r9, -1
bne loopRB
mtspr 8, r27
bclr 20, 0 /* return (r10) to caller */
/*
* spdWriteByte writes bits 24 - 31 of r10 to I2C.
* r8 contains bit mask 0x80
*/
spdWriteByte:
mfspr r27, 8 /* save link register */
li r9, 0x08 /* write octet */
and. r5, r10, r8
bne sWB1
stb r7, 0(r30) /* set SDA to _0_ */
eieio
b sWB2
sWB1:
stb r12, 0(r30) /* set SDA to _1_ */
eieio
sWB2:
stb r6, 1(r30) /* set GPIO to output */
eieio
loopWB:
and. r5, r10, r8
bne sWB3
stb r7, 0(r30) /* set SDA to _0_ */
eieio
b sWB4
sWB3:
stb r12, 0(r30) /* set SDA to _1_ */
eieio
sWB4:
bl waitSpd
and. r5, r10, r8
bne sWB5
stb r4, 0(r30) /* set SDA to _0_ and SCL */
eieio
b sWB6
sWB5:
stb r6, 0(r30) /* set SDA to _1_ and SCL */
eieio
sWB6:
bl waitSpd
and. r5, r10, r8
bne sWB7
stb r7, 0(r30) /* set SDA to _0_ and reset SCL */
eieio
b sWB8
sWB7:
stb r12, 0(r30) /* set SDA to _1_ and reset SCL */
eieio
sWB8:
bl waitSpd
rlwinm r10, r10, 1, 0, 31 /* next bit */
addic. r9, r9, -1
bne loopWB
mtspr 8, r27
bclr 20, 0 /* return to caller */
/*
* Read ACK from SPD, return value in r10
*/
spdReadAck:
mfspr r27, 8 /* save link register */
stb r4, 1(r30) /* set GPIO to output */
eieio
stb r7, 0(r30) /* reset SDA and SCL */
eieio
bl waitSpd
stb r4, 0(r30) /* set SCL */
eieio
bl waitSpd
lbz r10, 0(r30) /* read GPIO Port 1 and mask SDA */
and r10, r10, r12
bl waitSpd
stb r7, 0(r30) /* reset SDA and SCL */
eieio
bl waitSpd
mtspr 8, r27
bclr 20, 0 /* return (r10) to caller */
spdWriteAck:
mfspr r27, 8
stb r12, 0(r30) /* set SCL */
eieio
stb r6, 1(r30) /* set GPIO to output */
eieio
bl waitSpd
stb r6, 0(r30) /* SDA and SCL */
eieio
bl waitSpd
stb r12, 0(r30) /* reset SCL */
eieio
bl waitSpd
mtspr 8, r27
bclr 20, 0 /* return to caller */
get_lnk_reg:
mflr r3 /* return link reg */
blr
/*
* Messages for console output
*/
.globl MessageBlock
MessageBlock:
Mok:
.ascii "OK\015\012\000"
Mfail:
.ascii "FAILED\015\012\000"
Mna:
.ascii "NA\015\012\000"
MinitLogo:
.ascii "\015\012*** ELTEC Elektronik, Mainz ***\015\012"
.ascii "\015\012Initialising RAM\015\012\000"
Mspd01:
.ascii " Reading SPD of bank0/1 ..... \000"
Mspd23:
.ascii " Reading SPD of bank2/3 ..... \000"
MfpmRam:
.ascii " RAM-Type: FPM \015\012\000"
MedoRam:
.ascii " RAM-Type: EDO \015\012\000"
MsdRam:
.ascii " RAM-Type: SDRAM \015\012\000"
Mactivate:
.ascii " Activating \000"
Mmbyte:
.ascii " MB .......... \000"
.align 4
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