asm_init.s

AT91RM9200的完整启动代码：包括loader, boot及U-boot三部分均已编译通过！欢迎下载使用！

/*
 * (C) Copyright 2001 ELTEC Elektronik AG
 * Frank Gottschling <[e-mail]>
 *
 * ELTEC BAB PPC RAM initialization
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <74xx_7xx.h>
#include <mpc106.h>
#include <version.h>

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

/*
 * This following contains the entry code for the initialization code
 * for the MPC 106, a PCI Bridge/Memory Controller.
 * Register usage:
 * r0  = ramtest scratch register, toggleError loop counter
 * r1  = 0xfec0 0cf8 CONFIG_ADDRESS
 * r2  = 0xfee0 0cfc CONFIG_DATA
 * r3  = scratch register, subroutine argument and return value, ramtest size
 * r4  = scratch register, spdRead clock mask, OutHex loop count
 * r5  = ramtest scratch register
 * r6  = toggleError 1st value, spdRead port mask
 * r7  = toggleError 2nd value, ramtest scratch register,
 *       spdRead scratch register (0x00)
 * r8  = ramtest scratch register, spdRead scratch register (0x80)
 * r9  = ramtest scratch register, toggleError loop end, OutHex digit
 * r10 = ramtest scratch register, spdWriteByte parameter,
 *        spdReadByte return value, printf pointer to COM1
 * r11 = startType
 * r12 = ramtest scratch register, spdRead data mask
 * r13 = pointer to message block
 * r14 = pointer to GOT
 * r15 = scratch register, SPD save
 * r16 = bank0 size, total memory size
 * r17 = bank1 size
 * r18 = bank2 size
 * r19 = bank3 size
 * r20 = MCCR1, MSAR1
 * r21 = MCCR3, MEAR1
 * r22 = MCCR4, MBER
 * r23 = EMSAR1
 * r24 = EMEAR1
 * r25 = save link register 1st level
 * r26 = save link register 2nd level
 * r27 = save link register 3rd level
 * r30 = pointer to GPIO for spdRead
 */


.globl board_asm_init
board_asm_init:
/*
 * setup pointer to message block
 */
    mflr    r25             /* save away link register */
    bl      get_lnk_reg     /* r3=addr of next instruction */
    subi    r4, r3, 8       /* r4=board_asm_init addr */
    addi    r13, r4, (MessageBlock-board_asm_init)
/*
 * dcache_disable
 */
    mfspr   r3, HID0
    li      r4, HID0_DCE
    andc    r3, r3, r4
    mr      r2, r3
    ori     r3, r3, HID0_DCI
    sync
    mtspr   HID0, r3
    mtspr   HID0, r2
    isync
    sync
/*
 * icache_disable
 */
    mfspr   r3, HID0
    li      r4, 0
    ori     r4, r4, HID0_ICE
    andc    r3, r3, r4
    sync
    mtspr   HID0, r3
/*
 * invalidate caches
 */
    ori     r3, r3, (HID0_ICE | HID0_ICFI | HID0_DCI | HID0_DCE)
    or      r4, r4, r3
    isync
    mtspr   HID0, r4
    andc    r4, r4, r3
    isync
    mtspr   HID0, r4
    isync
/*
 * icache_enable
 */
    mfspr   r3, HID0
    ori     r3, r3, (HID0_ICE | HID0_ICFI)
    sync
    mtspr   HID0, r3

    lis     r1, 0xfec0
    ori     r1, r1, 0x0cf8
    lis     r2, 0xfee0
    ori     r2, r2, 0xcfc

#ifdef CFG_ADDRESS_MAP_A
/*
 * Switch to address map A if necessary.
 */
    lis     r3, MPC106_REG@h
    ori     r3, r3, PCI_PICR1
    stwbrx  r3, 0, r1
    sync
    lwbrx   r4, 0, r2
    sync
    lis     r0, PICR1_XIO_MODE@h
    ori     r0, r0, PICR1_XIO_MODE@l
    andc    r4, r4, r0
    lis     r0, PICR1_ADDRESS_MAP@h
    ori     r0, r0, PICR1_ADDRESS_MAP@l
    or      r4, r4, r0
    stwbrx  r4, 0, r2
    sync
#endif

/*
 * Do the init for the SIO.
 */
    bl      .sioInit

    addi    r3, r13, (MinitLogo-MessageBlock)
    bl      Printf

    addi    r3, r13, (Mspd01-MessageBlock)
    bl      Printf
/*
 * Memory cofiguration using SPD information stored on the SODIMMs
 */
    li      r17, 0
    li      r18, 0
    li      r19, 0

    li      r3, 0x0002          /* get RAM type from spd for bank0/1 */
    bl      spdRead

    cmpi    0, 0, r3, -1        /* error ? */
    bne     noSpdError

    addi    r3, r13, (Mfail-MessageBlock)
    bl      Printf

    li      r6, 0xe0            /* error codes in r6 and r7  */
    li      r7, 0x00
    b       toggleError         /* fail - loop forever */

noSpdError:
    mr      r15, r3             /* save r3 */

    addi    r3, r13, (Mok-MessageBlock)
    bl      Printf

    cmpli   0, 0, r15, 0x0001   /* FPM ? */
    beq     configFPM
    cmpli   0, 0, r15, 0x0002   /* EDO ? */
    beq     configEDO
    cmpli   0, 0, r15, 0x0004   /* SDRAM ? */
    beq     configSDRAM

    li      r6, 0xe0            /* error codes in r6 and r7  */
    li      r7, 0x01
    b       toggleError         /* fail - loop forever */

configSDRAM:
    addi    r3, r13, (MsdRam-MessageBlock)
    bl      Printf
/*
 * set the Memory Configuration Reg. 1
 */
    li      r3, 0x001f          /* get bank size from spd bank0/1 */
    bl      spdRead

    andi.   r3, r3, 0x0038
    beq     SD16MB2B

    li      r3, 0x0011          /* get number of internal banks */
                                /* from spd for bank0/1 */
    bl      spdRead

    cmpli   0, 0, r3, 0x02
    beq     SD64MB2B

    cmpli   0, 0, r3, 0x04
    beq     SD64MB4B

    li      r6, 0xe0            /* error codes in r6 and r7  */
    li      r7, 0x02
    b       toggleError         /* fail - loop forever */

SD64MB2B:
    li      r20, 0x0005         /* 64-Mbit SDRAM 2 banks */
    b       SDRow2nd

SD64MB4B:
    li      r20, 0x0000         /* 64-Mbit SDRAM 4 banks */
    b       SDRow2nd

SD16MB2B:
    li      r20, 0x000f         /* 16-Mbit SDRAM 2 banks */

SDRow2nd:
    li      r3, 0x0102          /* get RAM type spd for bank2/3 */
    bl      spdRead

    cmpli   0, 0, r3, 0x0004
    bne     S2D64MB4B           /* bank2/3 isn't present or no SDRAM */

    li      r3, 0x011f          /* get bank size from spd bank2/3 */
    bl      spdRead

    andi.   r3, r3, 0x0038
    beq     S2D16MB2B
/*
 * set the Memory Configuration Reg. 2
 */
    li      r3, 0x0111          /* get number of internal banks */
                                /* from spd for bank2/3 */
    bl      spdRead

    cmpli   0, 0, r3, 0x02
    beq     S2D64MB2B

    cmpli   0, 0, r3, 0x04
    beq     S2D64MB4B

    li      r6, 0xe0            /* error codes in r6 and r7 */
    li      r7, 0x03
    b       toggleError         /* fail - loop forever */

S2D64MB2B:
    ori     r20, r20, 0x0050    /* 64-Mbit SDRAM 2 banks */
    b       S2D64MB4B

S2D16MB2B:
    ori     r20, r20, 0x00f0    /* 16-Mbit SDRAM 2 banks */

/*
 * set the Memory Configuration Reg. 3
 */
S2D64MB4B:
    lis     r21, 0x8630         /* BSTOPRE = 0x80, REFREC = 6, */
                                /* RDLAT = 3 */

/*
 * set the Memory Configuration Reg. 4
 */
    lis     r22, 0x2430         /* PRETOACT = 2, ACTOPRE = 4, */
                                /* WCBUF = 1, RCBUF = 1 */
    ori     r22, r22, 0x2220    /* SDMODE = 0x022, ACTORW = 2 */

/*
 * get the size of bank 0-3
 */
    li      r3, 0x001f          /* get bank size from spd bank0/1 */
    bl      spdRead

    rlwinm  r16, r3, 2, 24, 29  /* calculate size in MByte */
                                /* (128 MB max.) */

    li      r3, 0x0005          /* get number of banks from spd */
                                /* for bank0/1 */
    bl      spdRead

    cmpi    0, 0, r3, 2         /* 2 banks ? */
    bne     SDRAMnobank1

    mr      r17, r16

SDRAMnobank1:
    addi    r3, r13, (Mspd23-MessageBlock)
    bl      Printf

    li      r3, 0x0102          /* get RAM type spd for bank2/3 */
    bl      spdRead

    cmpli   0, 0, r3, 0x0001    /* FPM ? */
    bne     noFPM23             /* handle as EDO */
    addi    r3, r13, (Mok-MessageBlock)
    bl      Printf
    addi    r3, r13, (MfpmRam-MessageBlock)
    bl      Printf
    b       configRAMcommon
noFPM23:
    cmpli   0, 0, r3, 0x0002    /* EDO ? */
    bne     noEDO23
    addi    r3, r13, (Mok-MessageBlock)
    bl      Printf
    addi    r3, r13, (MedoRam-MessageBlock)
    bl      Printf
    b       configRAMcommon
noEDO23:
    cmpli   0, 0, r3, 0x0004    /* SDRAM ? */
    bne    noSDRAM23
    addi    r3, r13, (Mok-MessageBlock)
    bl      Printf
    addi    r3, r13, (MsdRam-MessageBlock)
    bl      Printf
    b       configSDRAM23
noSDRAM23:
    addi    r3, r13, (Mna-MessageBlock)
    bl      Printf
    b       configRAMcommon     /* bank2/3 isn't present or no SDRAM */

configSDRAM23:
    li      r3, 0x011f          /* get bank size from spd bank2/3 */
    bl      spdRead

    rlwinm  r18, r3, 2, 24, 29  /* calculate size in MByte */
                                /* (128 MB max.) */

    li      r3, 0x0105          /* get number of banks from */
                                /* spd bank0/1 */
    bl      spdRead

    cmpi    0, 0, r3, 2         /* 2 banks ? */
    bne     SDRAMnobank3

    mr    r19, r18

SDRAMnobank3:
    b       configRAMcommon

configFPM:
    addi    r3, r13, (MfpmRam-MessageBlock)
    bl      Printf
    b       configEDO0
/*
 * set the Memory Configuration Reg. 1
 */
configEDO:
    addi    r3, r13, (MedoRam-MessageBlock)
    bl      Printf
configEDO0:
    lis     r20, MCCR1_TYPE_EDO@h

getSpdRowBank01:
    li      r3, 0x0003          /* get number of row bits from */
                                /* spd from bank0/1 */
    bl      spdRead
    ori     r20, r20, (MCCR1_BK0_9BITS | MCCR1_BK1_9BITS)
    cmpli   0, 0, r3, 0x0009    /* bank0 -  9 row bits */
    beq     getSpdRowBank23

    ori     r20, r20, (MCCR1_BK0_10BITS | MCCR1_BK1_10BITS)
    cmpli   0, 0, r3, 0x000a    /* bank0 -  10 row bits */
    beq     getSpdRowBank23

    ori     r20, r20, (MCCR1_BK0_11BITS | MCCR1_BK1_11BITS)
    cmpli   0, 0, r3, 0x000b    /* bank0 -  11 row bits */
    beq     getSpdRowBank23

    ori     r20, r20, (MCCR1_BK0_12BITS | MCCR1_BK1_12BITS)
    cmpli   0, 0, r3, 0x000c    /* bank0 -  12 row bits */
    beq     getSpdRowBank23

    cmpli   0, 0, r3, 0x000d    /* bank0 -  13 row bits */
    beq     getSpdRowBank23

    li      r6, 0xe0            /* error codes in r6 and r7 */
    li      r7, 0x10
    b       toggleError         /* fail - loop forever */

getSpdRowBank23:
    li     r3, 0x0103           /* get number of row bits from */
                                /* spd for bank2/3 */
    bl      spdRead

    ori     r20, r20, (MCCR1_BK2_9BITS | MCCR1_BK3_9BITS)
    cmpli   0, 0, r3, 0x0009    /* bank0 -  9 row bits */
    beq     writeRowBits

    ori     r20, r20, (MCCR1_BK2_10BITS | MCCR1_BK3_10BITS)
    cmpli   0, 0, r3, 0x000a    /* bank0 -  10 row bits */
    beq     writeRowBits

    ori     r20, r20, (MCCR1_BK2_11BITS | MCCR1_BK3_11BITS)
    cmpli   0, 0, r3, 0x000b    /* bank0 -  11 row bits */
    beq     writeRowBits

    ori     r20, r20, (MCCR1_BK2_12BITS | MCCR1_BK3_12BITS)

/*
 * set the Memory Configuration Reg. 3
 */
writeRowBits:
    lis     r21, 0x000a         /* CPX = 1, RAS6P = 4 */
    ori     r21, r21, 0x2293    /* CAS5 = 2, CP4 = 1, */
                                /* CAS3 = 2, RCD2 = 2, RP = 3 */
/*
 * set the Memory Configuration Reg. 4
 */
    lis     r22, 0x0010         /* all SDRAM parameter 0, */
                                /* WCBUF flow through, */
                                /* RCBUF registered */
/*
 * get the size of bank 0-3
 */
    li      r3, 0x0003          /* get row bits from spd  bank0/1 */
    bl      spdRead

    li      r16, 0              /* bank size is: */
                                /* (8*2^row*2^column)/0x100000 MB */
    ori     r16, r16, 0x8000
    rlwnm   r16, r16, r3, 0, 31

    li      r3, 0x0004          /* get column bits from spd bank0/1 */
    bl      spdRead

    rlwnm   r16, r16, r3, 0, 31

    li      r3, 0x0005          /* get number of banks from */
                                /* spd for bank0/1 */
    bl      spdRead

    cmpi    0, 0, r3, 2         /* 2 banks ? */
    bne     EDOnobank1

    mr      r17, r16

EDOnobank1:
    addi    r3, r13, (Mspd23-MessageBlock)
    bl      Printf

    li      r3, 0x0102          /* get RAM type spd for bank2/3 */
    bl      spdRead

    cmpli   0, 0, r3, 0x0001    /* FPM ? */
    bne     noFPM231            /* handle as EDO */
    addi    r3, r13, (Mok-MessageBlock)
    bl      Printf
    addi    r3, r13, (MfpmRam-MessageBlock)
    bl      Printf
    b       EDObank2
noFPM231:
    cmpli   0, 0, r3, 0x0002    /* EDO ? */
    bne     noEDO231
    addi    r3, r13, (Mok-MessageBlock)
    bl      Printf
    addi    r3, r13, (MedoRam-MessageBlock)
    bl      Printf
    b       EDObank2
noEDO231:
    cmpli   0, 0, r3, 0x0004    /* SDRAM ? */
    bne     noSDRAM231
    addi    r3, r13, (Mok-MessageBlock)
    bl      Printf
    addi    r3, r13, (MsdRam-MessageBlock)
    bl      Printf
    b       configRAMcommon
noSDRAM231:
    addi    r3, r13, (Mfail-MessageBlock)
    bl      Printf
    b       configRAMcommon     /* bank2/3 isn't present or no SDRAM */

EDObank2:
    li      r3, 0x0103          /* get row bits from spd for bank2/3 */
    bl      spdRead

    li      r18, 0              /* bank size is: */
                                /* (8*2^row*2^column)/0x100000 MB */
    ori     r18, r18, 0x8000
    rlwnm   r18, r18, r3, 0, 31

    li      r3, 0x0104          /* get column bits from spd bank2/3 */
    bl      spdRead