hermes.c

AT91RM9200的完整启动代码：包括loader, boot及U-boot三部分均已编译通过！欢迎下载使用！

	immr->im_cpm.cp_pbodr &= ~reg;
	immr->im_cpm.cp_pbdat &= ~reg;	/* all 0 */
	immr->im_cpm.cp_pbdir |= reg;

	/* Check hardware revision */
	if ((immr->im_ioport.iop_pcdat & 0x0003) == 0x0003) {
		/*
		 * Revision 3.x hardware
		 */
		revision = 3;

		immr->im_ioport.iop_pcdat = 0x0240;
		immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14);	/* = 0x0246 */
		immr->im_ioport.iop_pcdat |= PC_REP_RES;
	} else {
		immr->im_ioport.iop_pcdat = 0x0002;
		immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_RES | PC_BIT14 | PC_BIT15);	/* = 0x0207 */

		if ((immr->im_ioport.iop_pcdat & PC_REP_SPD) == 0) {
			/*
			 * Revision 2.x hardware: PC9 connected to PB21
			 */
			revision = 2;

			if (ethspeed == 0) {
				/* both 10 and 100 Mbps allowed:
				 * select 10 Mbps and autonegotiation
				 */
				puts ("  [10+100]");
				immr->im_cpm.cp_pbdat = 0;	/* SPD1:SPD0 = 0:0 - autonegot. */
				speed = 10;
			} else if (ethspeed == 10) {
				/* we are asked for 10 Mbps,
				 * so select 10 Mbps
				 */
				puts ("  [10]");
				immr->im_cpm.cp_pbdat = 0;	/* ??? */
				speed = 10;
			} else {
				/* anything else:
				 * select 100 Mbps
				 */
				puts ("  [100]");
				immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
				/* SPD1:SPD0 = 1:1 - 100 Mbps */
				speed = 100;
			}
			immr->im_ioport.iop_pcdat |= (PC_REP_RES | PC_BIT14);

			/* must be run from RAM  */
			/* start_lxt980 (speed); */
		/*************************/
		} else {
			/*
			 * Revision 1.x hardware
			 */
			revision = 1;

			immr->im_ioport.iop_pcdat = PC_REP_MGRPRS | PC_BIT14;	/* = 0x0202 */
			immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14 | PC_BIT15);	/* = 0x0247 */

			if (ethspeed == 0) {
				/* both 10 and 100 Mbps allowed:
				 * select 100 Mbps and autonegotiation
				 */
				puts ("  [10+100]");
				immr->im_cpm.cp_pbdat = 0;	/* SPD1:SPD0 = 0:0 - autonegot. */
				immr->im_ioport.iop_pcdat |= PC_REP_SPD;
			} else if (ethspeed == 10) {
				/* we are asked for 10 Mbps,
				   * so select 10 Mbps
				 */
				puts ("  [10]");
				immr->im_cpm.cp_pbdat = PC_REP_SPD0;	/* SPD1:SPD0 = 0:1 - 10 Mbps */
			} else {
				/* anything else:
				   * select 100 Mbps
				 */
				puts ("  [100]");
				immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
				/* SPD1:SPD0 = 1:1 - 100 Mbps */
				immr->im_ioport.iop_pcdat |= PC_REP_SPD;
			}

			immr->im_ioport.iop_pcdat |= PC_REP_RES;
		}
	}
	SHOW_BOOT_PROGRESS (0x00);

	return ((revision << 16) | (speed & 0xFFFF));
}

/* ------------------------------------------------------------------------- */

#define SCC_SM		1			/* Index => SCC2 */
#define	PROFF		PROFF_SCC2

#define SMI_MSGLEN	8			/* Length of SMI Messages        */

#define PHYGPCR_ADDR	0x109	/* Port Enable               */
#define PHYPCR_ADDR	0x132		/* PHY Port Control Reg. (port 1)    */
#define LEDPCR_ADDR	0x141		/* LED Port Control Reg.         */
#define RPRESET_ADDR	0x144	/* Repeater Reset            */

#define PHYPCR_SPEED	0x2000	/* on for 100 Mbps, off for 10 Mbps  */
#define PHYPCR_AN	0x1000		/* on to enable  Auto-Negotiation    */
#define PHYPCR_REST_AN	0x0200	/* on to restart Auto-Negotiation    */
#define PHYPCR_FDX	0x0100		/* on for Full Duplex, off for HDX   */
#define PHYPCR_COLT	0x0080		/* on to enable COL signal test      */

/* ------------------------------------------------------------------------- */

/*
 * Must run from RAM:
 * uses parameter RAM area which is used for stack while running from ROM
 */
void hermes_start_lxt980 (int speed)
{
	volatile immap_t *immr = (immap_t *) CFG_IMMR;
	volatile cpm8xx_t *cp = (cpm8xx_t *) & (immr->im_cpm);
	volatile scc_t *sp = (scc_t *) & (cp->cp_scc[SCC_SM]);
	volatile cbd_t *bd;
	volatile hdlc_pram_t *hp;
	uchar smimsg[SMI_MSGLEN];
	ushort phypcrval;
	uint bd_off;
	int pnr;

	printf ("LXT9880: %3d Mbps\n", speed);

	immr->im_ioport.iop_paodr |= 0x0008;	/* init PAODR: PA12 (TXD2) open drain */
	immr->im_ioport.iop_papar |= 0x400c;	/* init PAPAR: TXD2, RXD2, BRGO4 */
	immr->im_ioport.iop_padir &= 0xbff3;	/* init PADIR: BRGO4 */
	immr->im_ioport.iop_padir |= 0x4000;

	/* get temporary BD; no need for permanent alloc */
	bd_off = dpram_base_align (8);

	bd = (cbd_t *) (immr->im_cpm.cp_dpmem + bd_off);

	bd->cbd_bufaddr = 0;
	bd->cbd_datlen = 0;
	bd->cbd_sc = BD_SC_WRAP | BD_SC_LAST | BD_SC_INTRPT | BD_SC_TC;

	/* init. baudrate generator BRG4 */
	cp->cp_brgc4 = (0x00010000 | (50 << 1));	/* output 1 MHz */

	cp->cp_sicr &= 0xFFFF00FF;	/* SICR: mask SCC2 */
	cp->cp_sicr |= 0x00001B00;	/* SICR: SCC2 clk BRG4 */

	/* init SCC_SM register */
	sp->scc_psmr = 0x0000;		/* init PSMR: no additional flags */
	sp->scc_todr = 0x0000;
	sp->scc_dsr = 0x7e7e;

	/* init. SCC_SM parameter area */
	hp = (hdlc_pram_t *) & cp->cp_dparam[PROFF];

	hp->tbase = bd_off;			/* offset from beginning of DPRAM */

	hp->rfcr = 0x18;
	hp->tfcr = 0x18;
	hp->mrblr = 10;

	hp->c_mask = 0x0000f0b8;
	hp->c_pres = 0x0000ffff;

	hp->disfc = 0;
	hp->crcec = 0;
	hp->abtsc = 0;
	hp->nmarc = 0;
	hp->retrc = 0;

	hp->mflr = 10;

	hp->rfthr = 1;

	hp->hmask = 0;
	hp->haddr1 = 0;
	hp->haddr2 = 0;
	hp->haddr3 = 0;
	hp->haddr4 = 0;

	cp->cp_cpcr = SCC_SM << 6 | 0x0001;	/* SCC_SM: init TX/RX params */
	while (cp->cp_cpcr & CPM_CR_FLG);

	/* clear all outstanding SCC events */
	sp->scc_scce = ~0;

	/* enable transmitter: GSMR_L: TPL=2(16bits), TPP=3(all ones), ENT */
	sp->scc_gsmrh = 0;
	sp->scc_gsmrl |= SCC_GSMRL_TPL_16 | SCC_GSMRL_TPP_ALL1 |
			SCC_GSMRL_ENT | SCC_GSMRL_MODE_HDLC;

#if 0
	smimsg[0] = 0x00;			/* CHIP/HUB ID */
	smimsg[1] = 0x38;			/* WRITE CMD */
	smimsg[2] = (RPRESET_ADDR << 4) & 0xf0;
	smimsg[3] = RPRESET_ADDR >> 4;
	smimsg[4] = 0x01;
	smimsg[5] = 0x00;
	smimsg[6] = 0x00;
	smimsg[7] = 0x00;

	send_smi_frame (sp, bd, smimsg);
#endif

	smimsg[0] = 0x7f;			/* BROADCAST */
	smimsg[1] = 0x34;			/* ASSIGN HUB ID */
	smimsg[2] = 0x00;
	smimsg[3] = 0x00;
	smimsg[4] = 0x00;			/* HUB ID = 0 */
	smimsg[5] = 0x00;
	smimsg[6] = 0x00;
	smimsg[7] = 0x00;

	send_smi_frame (sp, bd, smimsg);

	smimsg[0] = 0x7f;			/* BROADCAST */
	smimsg[1] = 0x3c;			/* SET ARBOUT TO 0 */
	smimsg[2] = 0x00;			/* ADDRESS = 0 */
	smimsg[3] = 0x00;
	smimsg[4] = 0x00;			/* DATA = 0 */
	smimsg[5] = 0x00;
	smimsg[6] = 0x00;
	smimsg[7] = 0x00;

	send_smi_frame (sp, bd, smimsg);

	if (speed == 100) {
		phypcrval = PHYPCR_SPEED;	/* 100 MBIT, disable autoneg. */
	} else {
		phypcrval = 0;			/* 10 MBIT, disable autoneg. */
	}

	/* send MSGs */
	for (pnr = 0; pnr < 8; pnr++) {
		smimsg[0] = 0x00;		/* CHIP/HUB ID */
		smimsg[1] = 0x38;		/* WRITE CMD */
		smimsg[2] = ((PHYPCR_ADDR + pnr) << 4) & 0xf0;
		smimsg[3] = (PHYPCR_ADDR + pnr) >> 4;
		smimsg[4] = (unsigned char) (phypcrval & 0xff);
		smimsg[5] = (unsigned char) (phypcrval >> 8);
		smimsg[6] = 0x00;
		smimsg[7] = 0x00;

		send_smi_frame (sp, bd, smimsg);
	}

	smimsg[0] = 0x00;			/* CHIP/HUB ID */
	smimsg[1] = 0x38;			/* WRITE CMD */
	smimsg[2] = (PHYGPCR_ADDR << 4) & 0xf0;
	smimsg[3] = PHYGPCR_ADDR >> 4;
	smimsg[4] = 0xff;			/* enable port 1-8 */
	smimsg[5] = 0x01;			/* enable MII1 (0x01) */
	smimsg[6] = 0x00;
	smimsg[7] = 0x00;

	send_smi_frame (sp, bd, smimsg);

	smimsg[0] = 0x00;			/* CHIP/HUB ID */
	smimsg[1] = 0x38;			/* WRITE CMD */
	smimsg[2] = (LEDPCR_ADDR << 4) & 0xf0;
	smimsg[3] = LEDPCR_ADDR >> 4;
	smimsg[4] = 0xaa;			/* Port 1-8 Conf.bits = 10 (Hardware control) */
	smimsg[5] = 0xaa;
	smimsg[6] = 0x00;
	smimsg[7] = 0x00;

	send_smi_frame (sp, bd, smimsg);

	/*
	 * Disable Transmitter (so that we can free the BD, too)
	 */
	sp->scc_gsmrl &= ~SCC_GSMRL_ENT;
}

/* ------------------------------------------------------------------------- */

static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
							uchar * msg)
{
#ifdef DEBUG
	unsigned hub, chip, cmd, length, addr;

	hub = msg[0] & 0x1F;
	chip = msg[0] >> 5;
	cmd = msg[1] & 0x1F;
	length = (msg[1] >> 5) | ((msg[2] & 0x0F) << 3);
	addr = (msg[2] >> 4) | (msg[3] << 4);

	printf ("SMI send: Hub %02x Chip %x Cmd %02x Len %d Addr %03x: "
			"%02x %02x %02x %02x\n",
			hub, chip, cmd, length, addr, msg[4], msg[5], msg[6], msg[7]);
#endif /* DEBUG */

	bd->cbd_bufaddr = (uint) msg;
	bd->cbd_datlen = SMI_MSGLEN;
	bd->cbd_sc |= BD_SC_READY;

	/* wait for msg transmitted */
	while ((sp->scc_scce & 0x0002) == 0);
	/* clear all events */
	sp->scc_scce = ~0;
}

/* ------------------------------------------------------------------------- */

void show_boot_progress (int status)
{
	volatile immap_t *immr = (immap_t *) CFG_IMMR;

	status ^= 0x0F;
	status = (status & 0x0F) << 14;
	immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status;
}

/* ------------------------------------------------------------------------- */