sacsng.c

AT91RM9200的完整启动代码：包括loader, boot及U-boot三部分均已编译通过！欢迎下载使用！

	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
	for (i = 0; i < 8; i++)
	    *ramaddr = c;

	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
	*ramaddr = c;

	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
	*ramaddr = c;
    }

    /* return total ram size */
    return (sdram_size * chipselects);
}

/*-----------------------------------------------------------------------
 * Board Control Functions
 */
void board_poweroff (void)
{
    while (1);		/* hang forever */
}


#ifdef CONFIG_MISC_INIT_R
/* ------------------------------------------------------------------------- */
int misc_init_r(void)
{
    /*
     * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
     */
    volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */);
    volatile ioport_t *iop  = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);

    int  reg;          /* I2C register value */
    char *ep;          /* Environment pointer */
    char str_buf[12] ; /* sprintf output buffer */
    int  sample_rate;  /* ADC/DAC sample rate */
    int  sample_64x;   /* Use  64/4 clocking for the ADC/DAC */
    int  sample_128x;  /* Use 128/4 clocking for the ADC/DAC */
    int  right_just;   /* Is the data to the DAC right justified? */
    int  mclk_divide;  /* MCLK Divide */

    /*
     * SACSng custom initialization:
     *    Start the ADC and DAC clocks, since the Crystal parts do not
     *    work on the I2C bus until the clocks are running.
     */

    sample_rate = INITIAL_SAMPLE_RATE;
    if ((ep = getenv("DaqSampleRate")) != NULL) {
        sample_rate = simple_strtol(ep, NULL, 10);
    }

    sample_64x  = INITIAL_SAMPLE_64X;
    sample_128x = INITIAL_SAMPLE_128X;
    if ((ep = getenv("Daq64xSampling")) != NULL) {
        sample_64x = simple_strtol(ep, NULL, 10);
	if (sample_64x) {
	    sample_128x = 0;
	}
	else {
	    sample_128x = 1;
	}
    }
    else {
        if ((ep = getenv("Daq128xSampling")) != NULL) {
	    sample_128x = simple_strtol(ep, NULL, 10);
	    if (sample_128x) {
	        sample_64x = 0;
	    }
	    else {
	        sample_64x = 1;
	    }
	}
    }

    /* 
     * Stop the clocks and wait for at least 1 LRCLK period
     * to make sure the clocking has really stopped.
     */
    Daq_Stop_Clocks();
    udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);

    /*
     * Initialize the clocks with the new rates
     */
    Daq_Init_Clocks(sample_rate, sample_64x);
    sample_rate = Daq_Get_SampleRate();

    /*
     * Start the clocks and wait for at least 1 LRCLK period
     * to make sure the clocking has become stable.
     */
    Daq_Start_Clocks(sample_rate);
    udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);

    sprintf(str_buf, "%d", sample_rate);
    setenv("DaqSampleRate", str_buf);

    if (sample_64x) {
        setenv("Daq64xSampling",  "1");
        setenv("Daq128xSampling", NULL);
    }
    else {
        setenv("Daq64xSampling",  NULL);
        setenv("Daq128xSampling", "1");
    }

    /* Display the ADC/DAC clocking information */
    Daq_Display_Clocks();

    /*
     * Determine the DAC data justification
     */

    right_just = INITIAL_RIGHT_JUST;
    if ((ep = getenv("DaqDACRightJustified")) != NULL) {
        right_just = simple_strtol(ep, NULL, 10);
    }

    sprintf(str_buf, "%d", right_just);
    setenv("DaqDACRightJustified", str_buf);

    /*
     * Determine the DAC MCLK Divide
     */

    mclk_divide = INITIAL_MCLK_DIVIDE;
    if ((ep = getenv("DaqDACMClockDivide")) != NULL) {
        mclk_divide = simple_strtol(ep, NULL, 10);
    }

    sprintf(str_buf, "%d", mclk_divide);
    setenv("DaqDACMClockDivide", str_buf);

    /*
     * Initializing the I2C address in the Crystal A/Ds:
     *
     * 1) Wait for VREF cap to settle (10uSec per uF)
     * 2) Release pullup on SDATA
     * 3) Write the I2C address to register 6
     * 4) Enable address matching by setting the MSB in register 7
     */

    printf("Initializing the ADC...\n");
    udelay(ADC_INITIAL_DELAY);		/* 10uSec per uF of VREF cap */

    iopa->pdat &= ~ADC_SDATA1_MASK;     /* release SDATA1 */
    udelay(ADC_SDATA_DELAY);		/* arbitrary settling time */

    i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR);	/* set address */
    i2c_reg_write(I2C_ADC_1_ADDR, 0x07,         /* turn on ADDREN */
		  ADC_REG7_ADDR_ENABLE);

    i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */
		  (sample_64x ? 0 : ADC_REG2_128x) |
		  ADC_REG2_HIGH_PASS_DIS |
		  ADC_REG2_SLAVE_MODE);

    reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F;
    if(reg != I2C_ADC_1_ADDR)
	printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n",
	       reg, I2C_ADC_1_ADDR);

    iopa->pdat &= ~ADC_SDATA2_MASK;	/* release SDATA2 */
    udelay(ADC_SDATA_DELAY);		/* arbitrary settling time */

    i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR);	/* set address (do not set ADDREN yet) */

    i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */
		  (sample_64x ? 0 : ADC_REG2_128x) |
		  ADC_REG2_HIGH_PASS_DIS |
		  ADC_REG2_SLAVE_MODE);

    reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F;
    if(reg != I2C_ADC_2_ADDR)
	printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n",
	       reg, I2C_ADC_2_ADDR);

    i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */
		  ADC_REG1_FRAME_START |
		  ADC_REG1_GROUND_CAL);

    i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */
		  (sample_64x ? 0 : ADC_REG2_128x) |
		  ADC_REG2_CAL |
		  ADC_REG2_HIGH_PASS_DIS |
		  ADC_REG2_SLAVE_MODE);

    udelay(ADC_CAL_DELAY);		/* a minimum of 4100 LRCLKs */
    i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00);	/* remove GNDCAL */

    /*
     * Now that we have synchronized the ADC's, enable address
     * selection on the second ADC as well as the first.
     */
    i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE);

    /*
     * Initialize the Crystal DAC
     *
     * Two of the config lines are used for I2C so we have to set them
     * to the proper initialization state without inadvertantly
     * sending an I2C "start" sequence.  When we bring the I2C back to
     * the normal state, we send an I2C "stop" sequence.
     */
    printf("Initializing the DAC...\n");

    /*
     * Bring the I2C clock and data lines low for initialization
     */
    I2C_SCL(0);
    I2C_DELAY;
    I2C_SDA(0);
    I2C_ACTIVE;
    I2C_DELAY;

    /* Reset the DAC */
    iopa->pdat &= ~DAC_RST_MASK;
    udelay(DAC_RESET_DELAY);

    /* Release the DAC reset */
    iopa->pdat |=  DAC_RST_MASK;
    udelay(DAC_INITIAL_DELAY);

    /*
     * Cause the DAC to:
     *     Enable control port (I2C mode)
     *     Going into power down
     */
    i2c_reg_write(I2C_DAC_ADDR, 0x05,
		  DAC_REG5_I2C_MODE |
		  DAC_REG5_POWER_DOWN);

    /*
     * Cause the DAC to:
     *     Enable control port (I2C mode)
     *     Going into power down
     *         . MCLK divide by 1
     *         . MCLK divide by 2
     */
    i2c_reg_write(I2C_DAC_ADDR, 0x05,
		  DAC_REG5_I2C_MODE |
		  DAC_REG5_POWER_DOWN |
		  (mclk_divide ? DAC_REG5_MCLK_DIV : 0));

    /*
     * Cause the DAC to:
     *     Auto-mute disabled
     *         . Format 0, left  justified 24 bits
     *         . Format 3, right justified 24 bits
     *     No de-emphasis
     *         . Single speed mode
     *         . Double speed mode
     */
    i2c_reg_write(I2C_DAC_ADDR, 0x01,
		  (right_just ? DAC_REG1_RIGHT_JUST_24BIT :
                                DAC_REG1_LEFT_JUST_24_BIT) |
		  DAC_REG1_DEM_NO |
		  (sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));

    sprintf(str_buf, "%d",
	    sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE);
    setenv("DaqDACFunctionalMode", str_buf);

    /*
     * Cause the DAC to:
     *     Enable control port (I2C mode)
     *     Remove power down
     *         . MCLK divide by 1
     *         . MCLK divide by 2
     */
    i2c_reg_write(I2C_DAC_ADDR, 0x05,
		  DAC_REG5_I2C_MODE |
		  (mclk_divide ? DAC_REG5_MCLK_DIV : 0));

    /*
     * Create a I2C stop condition:
     *     low->high on data while clock is high.
     */
    I2C_SCL(1);
    I2C_DELAY;
    I2C_SDA(1);
    I2C_DELAY;
    I2C_TRISTATE;

    printf("\n");

#ifdef CONFIG_SHOW_BOOT_PROGRESS
    /*
     * Turn off the RED fail LED now that we are up and running.
     */
    status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
#endif

    return 0;
}

#ifdef CONFIG_SHOW_BOOT_PROGRESS
/*
 * Show boot status: flash the LED if something goes wrong, indicating
 * that last thing that worked and thus, by implication, what is broken.
 *
 * This stores the last OK value in RAM so this will not work properly
 * before RAM is initialized.  Since it is being used for indicating
 * boot status (i.e. after RAM is initialized), that is OK.
 */
static void flash_code(uchar number, uchar modulo, uchar digits)
{
    int   j;

    /*
     * Recursively do upper digits.
     */
    if(digits > 1) {
        flash_code(number / modulo, modulo, digits - 1);
    }

    number = number % modulo;

    /*
     * Zero is indicated by one long flash (dash).
     */
    if(number == 0) {
        status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
        udelay(1000000);
        status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
        udelay(200000);
    } else {
        /*
         * Non-zero is indicated by short flashes, one per count.
         */
        for(j = 0; j < number; j++) {
            status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
            udelay(100000);
            status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
            udelay(200000);
        }
    }
    /*
     * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total
     */
    udelay(700000);
}

static int last_boot_progress;

void show_boot_progress (int status)
{
    if(status != -1) {
        last_boot_progress = status;
    } else {
        /*
         * Houston, we have a problem.  Blink the last OK status which
         * indicates where things failed.
         */
        status_led_set(STATUS_LED_RED, STATUS_LED_ON);
        flash_code(last_boot_progress, 5, 3);
        udelay(1000000);
        status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING);
    }
}
#endif /* CONFIG_SHOW_BOOT_PROGRESS */


/*
 * The following are used to control the SPI chip selects for the SPI command.
 */
#if (CONFIG_COMMANDS & CFG_CMD_SPI)

#define SPI_ADC_CS_MASK	0x00000800
#define SPI_DAC_CS_MASK	0x00001000

void spi_adc_chipsel(int cs)
{
    volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);

    if(cs)
	iopd->pdat &= ~SPI_ADC_CS_MASK;	/* activate the chip select */
    else
	iopd->pdat |=  SPI_ADC_CS_MASK;	/* deactivate the chip select */
}

void spi_dac_chipsel(int cs)
{
    volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);

    if(cs)
	iopd->pdat &= ~SPI_DAC_CS_MASK;	/* activate the chip select */
    else
	iopd->pdat |=  SPI_DAC_CS_MASK;	/* deactivate the chip select */
}

/*
 * The SPI command uses this table of functions for controlling the SPI
 * chip selects: it calls the appropriate function to control the SPI
 * chip selects.
 */
spi_chipsel_type spi_chipsel[] = {
	spi_adc_chipsel,
	spi_dac_chipsel
};
int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);

#endif /* CFG_CMD_SPI */

#endif /* CONFIG_MISC_INIT_R */