processor.h

AT91RM9200的完整启动代码：包括loader, boot及U-boot三部分均已编译通过！欢迎下载使用！

#define	  TCR_WRC(x)		(((x)&0x3)<<28)	/* WDT Reset Control */
#define	    WRC_NONE		0		/* No reset will occur */
#define	    WRC_CORE		1		/* Core reset will occur */
#define	    WRC_CHIP		2		/* Chip reset will occur */
#define	    WRC_SYSTEM		3		/* System reset will occur */
#define	  TCR_WIE		0x08000000	/* WDT Interrupt Enable */
#define	  TCR_PIE		0x04000000	/* PIT Interrupt Enable */
#define	  TCR_FP(x)		(((x)&0x3)<<24)	/* FIT Period */
#define	    FP_2_9		0		/* 2^9 clocks */
#define	    FP_2_13		1		/* 2^13 clocks */
#define	    FP_2_17		2		/* 2^17 clocks */
#define	    FP_2_21		3		/* 2^21 clocks */
#define	  TCR_FIE		0x00800000	/* FIT Interrupt Enable */
#define	  TCR_ARE		0x00400000	/* Auto Reload Enable */
#define	SPRN_THRM1	0x3FC	/* Thermal Management Register 1 */
#define	  THRM1_TIN		(1<<0)
#define	  THRM1_TIV		(1<<1)
#define	  THRM1_THRES		(0x7f<<2)
#define	  THRM1_TID		(1<<29)
#define	  THRM1_TIE		(1<<30)
#define	  THRM1_V		(1<<31)
#define	SPRN_THRM2	0x3FD	/* Thermal Management Register 2 */
#define	SPRN_THRM3	0x3FE	/* Thermal Management Register 3 */
#define	  THRM3_E		(1<<31)
#define	SPRN_TSR	0x3D8	/* Timer Status Register */
#define	  TSR_ENW		0x80000000	/* Enable Next Watchdog */
#define	  TSR_WIS		0x40000000	/* WDT Interrupt Status */
#define	  TSR_WRS(x)		(((x)&0x3)<<28)	/* WDT Reset Status */
#define	    WRS_NONE		0		/* No WDT reset occurred */
#define	    WRS_CORE		1		/* WDT forced core reset */
#define	    WRS_CHIP		2		/* WDT forced chip reset */
#define	    WRS_SYSTEM		3		/* WDT forced system reset */
#define	  TSR_PIS		0x08000000	/* PIT Interrupt Status */
#define	  TSR_FIS		0x04000000	/* FIT Interrupt Status */
#define	SPRN_UMMCR0	0x3A8	/* User Monitor Mode Control Register 0 */
#define	SPRN_UMMCR1	0x3AC	/* User Monitor Mode Control Register 0 */
#define	SPRN_UPMC1	0x3A9	/* User Performance Counter Register 1 */
#define	SPRN_UPMC2	0x3AA	/* User Performance Counter Register 2 */
#define	SPRN_UPMC3	0x3AD	/* User Performance Counter Register 3 */
#define	SPRN_UPMC4	0x3AE	/* User Performance Counter Register 4 */
#define	SPRN_USIA	0x3AB	/* User Sampled Instruction Address Register */
#define	SPRN_XER	0x001	/* Fixed Point Exception Register */
#define	SPRN_ZPR	0x3B0	/* Zone Protection Register */

/* Short-hand versions for a number of the above SPRNs */

#define	CTR	SPRN_CTR	/* Counter Register */
#define	DAR	SPRN_DAR	/* Data Address Register */
#define	DABR	SPRN_DABR	/* Data Address Breakpoint Register */
#define	DBAT0L	SPRN_DBAT0L	/* Data BAT 0 Lower Register */
#define	DBAT0U	SPRN_DBAT0U	/* Data BAT 0 Upper Register */
#define	DBAT1L	SPRN_DBAT1L	/* Data BAT 1 Lower Register */
#define	DBAT1U	SPRN_DBAT1U	/* Data BAT 1 Upper Register */
#define	DBAT2L	SPRN_DBAT2L	/* Data BAT 2 Lower Register */
#define	DBAT2U	SPRN_DBAT2U	/* Data BAT 2 Upper Register */
#define	DBAT3L	SPRN_DBAT3L	/* Data BAT 3 Lower Register */
#define	DBAT3U	SPRN_DBAT3U	/* Data BAT 3 Upper Register */
#define	DCMP	SPRN_DCMP      	/* Data TLB Compare Register */
#define	DEC	SPRN_DEC       	/* Decrement Register */
#define	DMISS	SPRN_DMISS     	/* Data TLB Miss Register */
#define	DSISR	SPRN_DSISR	/* Data Storage Interrupt Status Register */
#define	EAR	SPRN_EAR       	/* External Address Register */
#define	HASH1	SPRN_HASH1	/* Primary Hash Address Register */
#define	HASH2	SPRN_HASH2	/* Secondary Hash Address Register */
#define	HID0	SPRN_HID0	/* Hardware Implementation Register 0 */
#define	HID1	SPRN_HID1	/* Hardware Implementation Register 1 */
#define	IABR	SPRN_IABR      	/* Instruction Address Breakpoint Register */
#define	IBAT0L	SPRN_IBAT0L	/* Instruction BAT 0 Lower Register */
#define	IBAT0U	SPRN_IBAT0U	/* Instruction BAT 0 Upper Register */
#define	IBAT1L	SPRN_IBAT1L	/* Instruction BAT 1 Lower Register */
#define	IBAT1U	SPRN_IBAT1U	/* Instruction BAT 1 Upper Register */
#define	IBAT2L	SPRN_IBAT2L	/* Instruction BAT 2 Lower Register */
#define	IBAT2U	SPRN_IBAT2U	/* Instruction BAT 2 Upper Register */
#define	IBAT3L	SPRN_IBAT3L	/* Instruction BAT 3 Lower Register */
#define	IBAT3U	SPRN_IBAT3U	/* Instruction BAT 3 Upper Register */
#define	ICMP	SPRN_ICMP	/* Instruction TLB Compare Register */
#define	IMISS	SPRN_IMISS	/* Instruction TLB Miss Register */
#define	IMMR	SPRN_IMMR      	/* PPC 860/821 Internal Memory Map Register */
#define	L2CR	SPRN_L2CR    	/* PPC 750 L2 control register */
#define	LR	SPRN_LR
#define	PVR	SPRN_PVR	/* Processor Version */
#define	RPA	SPRN_RPA	/* Required Physical Address Register */
#define	SDR1	SPRN_SDR1      	/* MMU hash base register */
#define	SPR0	SPRN_SPRG0	/* Supervisor Private Registers */
#define	SPR1	SPRN_SPRG1
#define	SPR2	SPRN_SPRG2
#define	SPR3	SPRN_SPRG3
#define	SPRG0   SPRN_SPRG0
#define	SPRG1   SPRN_SPRG1
#define	SPRG2   SPRN_SPRG2
#define	SPRG3   SPRN_SPRG3
#define	SRR0	SPRN_SRR0	/* Save and Restore Register 0 */
#define	SRR1	SPRN_SRR1	/* Save and Restore Register 1 */
#define	TBRL	SPRN_TBRL	/* Time Base Read Lower Register */
#define	TBRU	SPRN_TBRU	/* Time Base Read Upper Register */
#define	TBWL	SPRN_TBWL	/* Time Base Write Lower Register */
#define	TBWU	SPRN_TBWU	/* Time Base Write Upper Register */
#define ICTC	1019
#define	THRM1	SPRN_THRM1	/* Thermal Management Register 1 */
#define	THRM2	SPRN_THRM2	/* Thermal Management Register 2 */
#define	THRM3	SPRN_THRM3	/* Thermal Management Register 3 */
#define	XER	SPRN_XER


/* Device Control Registers */

#define	DCRN_BEAR	0x090	/* Bus Error Address Register */
#define	DCRN_BESR	0x091	/* Bus Error Syndrome Register */
#define	  BESR_DSES    	0x80000000	/* Data-Side Error Status */
#define	  BESR_DMES	0x40000000	/* DMA Error Status */
#define	  BESR_RWS	0x20000000	/* Read/Write Status */
#define	  BESR_ETMASK	0x1C000000	/* Error Type */
#define	    ET_PROT	0
#define	    ET_PARITY	1
#define	    ET_NCFG	2
#define	    ET_BUSERR	4
#define	    ET_BUSTO	6
#define	DCRN_DMACC0	0x0C4	/* DMA Chained Count Register 0 */
#define	DCRN_DMACC1	0x0CC	/* DMA Chained Count Register 1 */
#define	DCRN_DMACC2	0x0D4	/* DMA Chained Count Register 2 */
#define	DCRN_DMACC3	0x0DC    /* DMA Chained Count Register 3 */
#define	DCRN_DMACR0	0x0C0    /* DMA Channel Control Register 0 */
#define	DCRN_DMACR1	0x0C8    /* DMA Channel Control Register 1 */
#define	DCRN_DMACR2	0x0D0    /* DMA Channel Control Register 2 */
#define	DCRN_DMACR3	0x0D8    /* DMA Channel Control Register 3 */
#define	DCRN_DMACT0	0x0C1    /* DMA Count Register 0 */
#define	DCRN_DMACT1	0x0C9    /* DMA Count Register 1 */
#define	DCRN_DMACT2	0x0D1    /* DMA Count Register 2 */
#define	DCRN_DMACT3	0x0D9    /* DMA Count Register 3 */
#define	DCRN_DMADA0	0x0C2    /* DMA Destination Address Register 0 */
#define	DCRN_DMADA1	0x0CA    /* DMA Destination Address Register 1 */
#define	DCRN_DMADA2	0x0D2    /* DMA Destination Address Register 2 */
#define	DCRN_DMADA3	0x0DA    /* DMA Destination Address Register 3 */
#define	DCRN_DMASA0	0x0C3    /* DMA Source Address Register 0 */
#define	DCRN_DMASA1	0x0CB    /* DMA Source Address Register 1 */
#define	DCRN_DMASA2	0x0D3    /* DMA Source Address Register 2 */
#define	DCRN_DMASA3	0x0DB    /* DMA Source Address Register 3 */
#define	DCRN_DMASR	0x0E0    /* DMA Status Register */
#define	DCRN_EXIER	0x042    /* External Interrupt Enable Register */
#define	  EXIER_CIE	0x80000000	/* Critical Interrupt Enable */
#define	  EXIER_SRIE	0x08000000	/* Serial Port Rx Int. Enable */
#define	  EXIER_STIE	0x04000000	/* Serial Port Tx Int. Enable */
#define	  EXIER_JRIE	0x02000000	/* JTAG Serial Port Rx Int. Enable */
#define	  EXIER_JTIE	0x01000000	/* JTAG Serial Port Tx Int. Enable */
#define	  EXIER_D0IE	0x00800000	/* DMA Channel 0 Interrupt Enable */
#define	  EXIER_D1IE	0x00400000	/* DMA Channel 1 Interrupt Enable */
#define	  EXIER_D2IE	0x00200000	/* DMA Channel 2 Interrupt Enable */
#define	  EXIER_D3IE	0x00100000	/* DMA Channel 3 Interrupt Enable */
#define	  EXIER_E0IE	0x00000010	/* External Interrupt 0 Enable */
#define	  EXIER_E1IE	0x00000008	/* External Interrupt 1 Enable */
#define	  EXIER_E2IE	0x00000004	/* External Interrupt 2 Enable */
#define	  EXIER_E3IE	0x00000002	/* External Interrupt 3 Enable */
#define	  EXIER_E4IE	0x00000001	/* External Interrupt 4 Enable */
#define	DCRN_EXISR	0x040    /* External Interrupt Status Register */
#define	DCRN_IOCR	0x0A0    /* Input/Output Configuration Register */
#define	  IOCR_E0TE	0x80000000
#define	  IOCR_E0LP	0x40000000
#define	  IOCR_E1TE	0x20000000
#define	  IOCR_E1LP	0x10000000
#define	  IOCR_E2TE	0x08000000
#define	  IOCR_E2LP	0x04000000
#define	  IOCR_E3TE	0x02000000
#define	  IOCR_E3LP	0x01000000
#define	  IOCR_E4TE	0x00800000
#define	  IOCR_E4LP	0x00400000
#define	  IOCR_EDT     	0x00080000
#define	  IOCR_SOR     	0x00040000
#define	  IOCR_EDO	0x00008000
#define	  IOCR_2XC	0x00004000
#define	  IOCR_ATC	0x00002000
#define	  IOCR_SPD	0x00001000
#define	  IOCR_BEM	0x00000800
#define	  IOCR_PTD	0x00000400
#define	  IOCR_ARE	0x00000080
#define	  IOCR_DRC	0x00000020
#define	  IOCR_RDM(x)	(((x) & 0x3) << 3)
#define	  IOCR_TCS	0x00000004
#define	  IOCR_SCS	0x00000002
#define	  IOCR_SPC	0x00000001


/* Processor Version Register */

/* Processor Version Register (PVR) field extraction */

#define	PVR_VER(pvr)  (((pvr) >>  16) & 0xFFFF)	/* Version field */
#define	PVR_REV(pvr)  (((pvr) >>   0) & 0xFFFF)	/* Revison field */

/*
 * IBM has further subdivided the standard PowerPC 16-bit version and
 * revision subfields of the PVR for the PowerPC 403s into the following:
 */

#define	PVR_FAM(pvr)	(((pvr) >> 20) & 0xFFF)	/* Family field */
#define	PVR_MEM(pvr)	(((pvr) >> 16) & 0xF)	/* Member field */
#define	PVR_CORE(pvr)	(((pvr) >> 12) & 0xF)	/* Core field */
#define	PVR_CFG(pvr)	(((pvr) >>  8) & 0xF)	/* Configuration field */
#define	PVR_MAJ(pvr)	(((pvr) >>  4) & 0xF)	/* Major revision field */
#define	PVR_MIN(pvr)	(((pvr) >>  0) & 0xF)	/* Minor revision field */

/* Processor Version Numbers */

#define	PVR_403GA	0x00200000
#define	PVR_403GB	0x00200100
#define	PVR_403GC	0x00200200
#define	PVR_403GCX	0x00201400
#define	PVR_405GP	0x40110000
#define	PVR_405GP_RB	0x40110040
#define	PVR_405GP_RC	0x40110082
#define	PVR_405GP_RD	0x401100C4
#define	PVR_405GP_RE	0x40110145  /* same as pc405cr rev c */
#define	PVR_405CR_RA	0x40110041
#define	PVR_405CR_RB	0x401100C5
#define	PVR_405CR_RC	0x40110145  /* same as pc405gp rev e */
#define	PVR_405GPR_RB	0x50910951
#define	PVR_440GP_RB	0x40120440
#define	PVR_440GP_RC	0x40120481
#define	PVR_405EP_RB	0x51210950
#define	PVR_601		0x00010000
#define	PVR_602		0x00050000
#define	PVR_603		0x00030000
#define	PVR_603e	0x00060000
#define	PVR_603ev	0x00070000
#define	PVR_603r	0x00071000
#define	PVR_604		0x00040000
#define	PVR_604e	0x00090000
#define	PVR_604r	0x000A0000
#define	PVR_620		0x00140000
#define	PVR_740		0x00080000
#define	PVR_750		PVR_740
#define	PVR_740P	0x10080000
#define	PVR_750P	PVR_740P
/*
 * For the 8xx processors, all of them report the same PVR family for
 * the PowerPC core. The various versions of these processors must be
 * differentiated by the version number in the Communication Processor
 * Module (CPM).
 */
#define	PVR_821		0x00500000
#define	PVR_823		PVR_821
#define	PVR_850		PVR_821
#define	PVR_860		PVR_821
#define	PVR_7400       	0x000C0000
#define	PVR_8240	0x00810100
#define	PVR_8260	PVR_8240


/* I am just adding a single entry for 8260 boards.  I think we may be
 * able to combine mbx, fads, rpxlite, bseip, and classic into a single
 * generic 8xx as well.  The boards containing these processors are either