gt64260r.h

AT91RM9200的完整启动代码：包括loader, boot及U-boot三部分均已编译通过！欢迎下载使用！

/* gt64260R.h - GT64260 Internal registers definition file */

/* Copyright - Galileo technology. */

#ifndef __INCgt64260rh
#define __INCgt64260rh

#ifndef GT64260
#define GT64260
#endif

/* CPU MASTER CONTROL REGISTER */
#define	CPU_CONFIGURATION	0x0
#define	CPU_MASTER_CONTROL	0x160

/****************************************/
/* Processor Address Space				*/
/****************************************/

/* Sdram's BAR'S */
#define SCS_0_LOW_DECODE_ADDRESS							0x008
#define SCS_0_HIGH_DECODE_ADDRESS							0x010
#define SCS_1_LOW_DECODE_ADDRESS							0x208
#define SCS_1_HIGH_DECODE_ADDRESS							0x210
#define SCS_2_LOW_DECODE_ADDRESS							0x018
#define SCS_2_HIGH_DECODE_ADDRESS							0x020
#define SCS_3_LOW_DECODE_ADDRESS							0x218
#define SCS_3_HIGH_DECODE_ADDRESS							0x220
/* Devices BAR'S */
#define CS_0_LOW_DECODE_ADDRESS							    0x028
#define CS_0_HIGH_DECODE_ADDRESS							0x030
#define CS_1_LOW_DECODE_ADDRESS							    0x228
#define CS_1_HIGH_DECODE_ADDRESS							0x230
#define CS_2_LOW_DECODE_ADDRESS							    0x248
#define CS_2_HIGH_DECODE_ADDRESS							0x250
#define CS_3_LOW_DECODE_ADDRESS							    0x038
#define CS_3_HIGH_DECODE_ADDRESS							0x040
#define BOOTCS_LOW_DECODE_ADDRESS							0x238
#define BOOTCS_HIGH_DECODE_ADDRESS							0x240

#define PCI_0I_O_LOW_DECODE_ADDRESS							0x048
#define PCI_0I_O_HIGH_DECODE_ADDRESS						0x050
#define PCI_0MEMORY0_LOW_DECODE_ADDRESS						0x058
#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS					0x060
#define PCI_0MEMORY1_LOW_DECODE_ADDRESS						0x080
#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS					0x088
#define PCI_0MEMORY2_LOW_DECODE_ADDRESS						0x258
#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS					0x260
#define PCI_0MEMORY3_LOW_DECODE_ADDRESS						0x280
#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS					0x288

#define PCI_1I_O_LOW_DECODE_ADDRESS							0x090
#define PCI_1I_O_HIGH_DECODE_ADDRESS						0x098
#define PCI_1MEMORY0_LOW_DECODE_ADDRESS						0x0a0
#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS					0x0a8
#define PCI_1MEMORY1_LOW_DECODE_ADDRESS						0x0b0
#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS					0x0b8
#define PCI_1MEMORY2_LOW_DECODE_ADDRESS						0x2a0
#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS					0x2a8
#define PCI_1MEMORY3_LOW_DECODE_ADDRESS						0x2b0
#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS					0x2b8


#define INTERNAL_SPACE_DECODE								0x068

#define CPU_0_LOW_DECODE_ADDRESS                            0x290
#define CPU_0_HIGH_DECODE_ADDRESS                           0x298
#define CPU_1_LOW_DECODE_ADDRESS                            0x2c0
#define CPU_1_HIGH_DECODE_ADDRESS                           0x2c8

#define PCI_0I_O_ADDRESS_REMAP								0x0f0
#define PCI_0MEMORY0_ADDRESS_REMAP  			   			0x0f8
#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP			   			0x320
#define PCI_0MEMORY1_ADDRESS_REMAP  			   			0x100
#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP			   			0x328
#define PCI_0MEMORY2_ADDRESS_REMAP  			   			0x2f8
#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP			   			0x330
#define PCI_0MEMORY3_ADDRESS_REMAP  			   			0x300
#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP			   			0x338

#define PCI_1I_O_ADDRESS_REMAP								0x108
#define PCI_1MEMORY0_ADDRESS_REMAP  				   		0x110
#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP				   		0x340
#define PCI_1MEMORY1_ADDRESS_REMAP  					   	0x118
#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP					   	0x348
#define PCI_1MEMORY2_ADDRESS_REMAP  					   	0x310
#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP					   	0x350
#define PCI_1MEMORY3_ADDRESS_REMAP  					   	0x318
#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP					   	0x358




/****************************************/
/* CPU Sync Barrier             		*/
/****************************************/

#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER					0x0c0
#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER					0x0c8


/****************************************/
/* CPU Access Protect             		*/
/****************************************/

#define CPU_LOW_PROTECT_ADDRESS_0                           0x180
#define CPU_HIGH_PROTECT_ADDRESS_0                          0x188
#define CPU_LOW_PROTECT_ADDRESS_1                           0x190
#define CPU_HIGH_PROTECT_ADDRESS_1                          0x198
#define CPU_LOW_PROTECT_ADDRESS_2                           0x1a0
#define CPU_HIGH_PROTECT_ADDRESS_2                          0x1a8
#define CPU_LOW_PROTECT_ADDRESS_3                           0x1b0
#define CPU_HIGH_PROTECT_ADDRESS_3                          0x1b8
#define CPU_LOW_PROTECT_ADDRESS_4                           0x1c0
#define CPU_HIGH_PROTECT_ADDRESS_4                          0x1c8
#define CPU_LOW_PROTECT_ADDRESS_5                           0x1d0
#define CPU_HIGH_PROTECT_ADDRESS_5                          0x1d8
#define CPU_LOW_PROTECT_ADDRESS_6                           0x1e0
#define CPU_HIGH_PROTECT_ADDRESS_6                          0x1e8
#define CPU_LOW_PROTECT_ADDRESS_7                           0x1f0
#define CPU_HIGH_PROTECT_ADDRESS_7                          0x1f8


/****************************************/
/*          Snoop Control          		*/
/****************************************/

#define SNOOP_BASE_ADDRESS_0                                0x380
#define SNOOP_TOP_ADDRESS_0                                 0x388
#define SNOOP_BASE_ADDRESS_1                                0x390
#define SNOOP_TOP_ADDRESS_1                                 0x398
#define SNOOP_BASE_ADDRESS_2                                0x3a0
#define SNOOP_TOP_ADDRESS_2                                 0x3a8
#define SNOOP_BASE_ADDRESS_3                                0x3b0
#define SNOOP_TOP_ADDRESS_3                                 0x3b8

/****************************************/
/*          CPU Error Report       		*/
/****************************************/

#define CPU_ERROR_ADDRESS_LOW 							    0x070
#define CPU_ERROR_ADDRESS_HIGH 							    0x078
#define CPU_ERROR_DATA_LOW                                  0x128
#define CPU_ERROR_DATA_HIGH                                 0x130
#define CPU_ERROR_PARITY                                    0x138
#define CPU_ERROR_CAUSE                                     0x140
#define CPU_ERROR_MASK                                      0x148

/****************************************/
/*          Pslave Debug           		*/
/****************************************/

#define X_0_ADDRESS                                         0x360
#define X_0_COMMAND_ID                                      0x368
#define X_1_ADDRESS                                         0x370
#define X_1_COMMAND_ID                                      0x378
#define WRITE_DATA_LOW                                      0x3c0
#define WRITE_DATA_HIGH                                     0x3c8
#define WRITE_BYTE_ENABLE                                   0x3e0
#define READ_DATA_LOW                                       0x3d0
#define READ_DATA_HIGH                                      0x3d8
#define READ_ID                                             0x3e8


/****************************************/
/* SDRAM and Device Address Space		*/
/****************************************/


/****************************************/
/* SDRAM Configuration			*/
/****************************************/


#define SDRAM_CONFIGURATION				0x448
#define SDRAM_OPERATION_MODE				0x474
#define SDRAM_ADDRESS_DECODE				0x47c
#define SDRAM_UMA_CONTROL				0x4a4
#define SDRAM_CROSS_BAR_CONTROL_LOW			0x4a8
#define SDRAM_CROSS_BAR_CONTROL_HIGH			0x4ac
#define SDRAM_CROSS_BAR_TIMEOUT				0x4b0
#define SDRAM_TIMING					0x4b4


/****************************************/
/* SDRAM Parameters			*/
/****************************************/

#define SDRAM_BANK0PARAMETERS				0x44C
#define SDRAM_BANK1PARAMETERS				0x450
#define SDRAM_BANK2PARAMETERS				0x454
#define SDRAM_BANK3PARAMETERS				0x458


/****************************************/
/* SDRAM Error Report 			*/
/****************************************/

#define SDRAM_ERROR_DATA_LOW                                0x484
#define SDRAM_ERROR_DATA_HIGH                               0x480
#define SDRAM_AND_DEVICE_ERROR_ADDRESS                      0x490
#define SDRAM_RECEIVED_ECC                                  0x488
#define SDRAM_CALCULATED_ECC                                0x48c
#define SDRAM_ECC_CONTROL                                   0x494
#define SDRAM_ECC_ERROR_COUNTER                             0x498


/****************************************/
/* SDunit Debug (for internal use)	*/
/****************************************/

#define X0_ADDRESS                                          0x500
#define X0_COMMAND_AND_ID                                   0x504
#define X0_WRITE_DATA_LOW                                   0x508
#define X0_WRITE_DATA_HIGH                                  0x50c
#define X0_WRITE_BYTE_ENABLE                                0x518
#define X0_READ_DATA_LOW                                    0x510
#define X0_READ_DATA_HIGH                                   0x514
#define X0_READ_ID                                          0x51c
#define X1_ADDRESS                                          0x520
#define X1_COMMAND_AND_ID                                   0x524
#define X1_WRITE_DATA_LOW                                   0x528
#define X1_WRITE_DATA_HIGH                                  0x52c
#define X1_WRITE_BYTE_ENABLE                                0x538
#define X1_READ_DATA_LOW                                    0x530
#define X1_READ_DATA_HIGH                                   0x534
#define X1_READ_ID                                          0x53c
#define X0_SNOOP_ADDRESS                                    0x540
#define X0_SNOOP_COMMAND                                    0x544
#define X1_SNOOP_ADDRESS                                    0x548
#define X1_SNOOP_COMMAND                                    0x54c



/****************************************/
/* Device Parameters					*/
/****************************************/

#define DEVICE_BANK0PARAMETERS								0x45c
#define DEVICE_BANK1PARAMETERS								0x460
#define DEVICE_BANK2PARAMETERS								0x464
#define DEVICE_BANK3PARAMETERS								0x468
#define DEVICE_BOOT_BANK_PARAMETERS							0x46c
#define DEVICE_CONTROL                                      0x4c0
#define DEVICE_CROSS_BAR_CONTROL_LOW                        0x4c8
#define DEVICE_CROSS_BAR_CONTROL_HIGH                       0x4cc
#define DEVICE_CROSS_BAR_TIMEOUT                            0x4c4


/****************************************/
/* Device Interrupt 					*/
/****************************************/

#define DEVICE_INTERRUPT_CAUSE                              0x4d0
#define DEVICE_INTERRUPT_MASK                               0x4d4
#define DEVICE_ERROR_ADDRESS                                0x4d8

/****************************************/
/* DMA Record							*/
/****************************************/

#define CHANNEL0_DMA_BYTE_COUNT						0x800
#define CHANNEL1_DMA_BYTE_COUNT	 							0x804
#define CHANNEL2_DMA_BYTE_COUNT	 							0x808
#define CHANNEL3_DMA_BYTE_COUNT	 							0x80C
#define CHANNEL4_DMA_BYTE_COUNT								0x900
#define CHANNEL5_DMA_BYTE_COUNT	 							0x904
#define CHANNEL6_DMA_BYTE_COUNT	 							0x908
#define CHANNEL7_DMA_BYTE_COUNT	 							0x90C
#define CHANNEL0_DMA_SOURCE_ADDRESS							0x810
#define CHANNEL1_DMA_SOURCE_ADDRESS							0x814
#define CHANNEL2_DMA_SOURCE_ADDRESS							0x818
#define CHANNEL3_DMA_SOURCE_ADDRESS							0x81C
#define CHANNEL4_DMA_SOURCE_ADDRESS							0x910
#define CHANNEL5_DMA_SOURCE_ADDRESS							0x914
#define CHANNEL6_DMA_SOURCE_ADDRESS							0x918
#define CHANNEL7_DMA_SOURCE_ADDRESS							0x91C
#define CHANNEL0_DMA_DESTINATION_ADDRESS					0x820
#define CHANNEL1_DMA_DESTINATION_ADDRESS					0x824
#define CHANNEL2_DMA_DESTINATION_ADDRESS					0x828
#define CHANNEL3_DMA_DESTINATION_ADDRESS					0x82C
#define CHANNEL4_DMA_DESTINATION_ADDRESS					0x920
#define CHANNEL5_DMA_DESTINATION_ADDRESS					0x924
#define CHANNEL6_DMA_DESTINATION_ADDRESS					0x928
#define CHANNEL7_DMA_DESTINATION_ADDRESS					0x92C
#define CHANNEL0NEXT_RECORD_POINTER							0x830
#define CHANNEL1NEXT_RECORD_POINTER							0x834
#define CHANNEL2NEXT_RECORD_POINTER							0x838
#define CHANNEL3NEXT_RECORD_POINTER							0x83C
#define CHANNEL4NEXT_RECORD_POINTER							0x930
#define CHANNEL5NEXT_RECORD_POINTER							0x934
#define CHANNEL6NEXT_RECORD_POINTER							0x938
#define CHANNEL7NEXT_RECORD_POINTER							0x93C
#define CHANNEL0CURRENT_DESCRIPTOR_POINTER					0x870
#define CHANNEL1CURRENT_DESCRIPTOR_POINTER					0x874
#define CHANNEL2CURRENT_DESCRIPTOR_POINTER					0x878
#define CHANNEL3CURRENT_DESCRIPTOR_POINTER					0x87C
#define CHANNEL4CURRENT_DESCRIPTOR_POINTER					0x970
#define CHANNEL5CURRENT_DESCRIPTOR_POINTER					0x974
#define CHANNEL6CURRENT_DESCRIPTOR_POINTER					0x978