ppmc8260.h

AT91RM9200的完整启动代码：包括loader, boot及U-boot三部分均已编译通过！欢迎下载使用！

 *     - 64 bit port size (60x bus only)
 *     - Data errors checking is disabled
 *     - Read and write access
 *     - SDRAM 60x bus
 *     - Access are handled by the memory controller according to MSEL
 *     - Not used for atomic operations
 *     - No data pipelining is done
 *     - Valid
 */
#define CFG_BR2_PRELIM	((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
			 BRx_PS_64			|\
			 BRx_MS_SDRAM_P			|\
			 BRx_V)

#define CFG_BR3_PRELIM	((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
			 BRx_PS_64			|\
			 BRx_MS_SDRAM_P			|\
			 BRx_V)

/* With a 128 MB DIMM, the OR2 is configured as follows:
 *
 *     - 128 MB
 *     - 4 internal banks per device
 *     - Row start address bit is A8 with PSDMR[PBI] = 0
 *     - 13 row address lines
 *     - Back-to-back page mode
 *     - Internal bank interleaving within save device enabled
 */

#define CFG_OR2_PRELIM	(MEG_TO_AM(CFG_SDRAM0_SIZE)	|\
			 ORxS_BPD_4			|\
			 ORxS_ROWST_PBI0_A7		|\
			 ORxS_NUMR_13)

#define CFG_OR3_PRELIM	(MEG_TO_AM(CFG_SDRAM1_SIZE)	|\
			 ORxS_BPD_4			|\
			 ORxS_ROWST_PBI0_A7		|\
			 ORxS_NUMR_13)


/*-----------------------------------------------------------------------
 * PSDMR - 60x Bus SDRAM Mode Register
 *     Ref: Section 10.3.3 on page 10-21
 *-----------------------------------------------------------------------
 */

/* With a 128 MB DIMM, the PSDMR is configured as follows:
 *
 *     - Page Based Interleaving,
 *     - Refresh Enable,
 *     - Normal Operation
 *     - Address Multiplexing where A5 is output on A14 pin
 *	 (A6 on A15, and so on),
 *     - use address pins A13-A15 as bank select,
 *     - A9 is output on SDA10 during an ACTIVATE command,
 *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 *	 is 3 clocks,
 *     - earliest timing for READ/WRITE command after ACTIVATE command is
 *	 2 clocks,
 *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 *     - External Address Multiplexing enabled
 *     - CAS Latency is 2.
 */
#define CFG_PSDMR	(PSDMR_RFEN	      |\
			 PSDMR_SDAM_A14_IS_A5 |\
			 PSDMR_BSMA_A13_A15   |\
			 PSDMR_SDA10_PBI0_A9  |\
			 PSDMR_RFRC_7_CLK     |\
			 PSDMR_PRETOACT_3W    |\
			 PSDMR_ACTTORW_2W     |\
			 PSDMR_LDOTOPRE_1C    |\
			 PSDMR_WRC_1C	      |\
			 PSDMR_EAMUX	      |\
			 PSDMR_CL_2)


#define CFG_PSRT	0x0e
#define CFG_MPTPR	MPTPR_PTP_DIV32


/*-----------------------------------------------------------------------
 * BR4 - Base Register
 *     Ref: Section 10.3.1 on page 10-14
 * OR4 - Option Register
 *     Ref: Section 10.3.2 on page 10-16
 *-----------------------------------------------------------------------
 */

/*
 * Bank 4 - On board SDRAM
 *
 */
/* With 16 MB of onboard SDRAM	BR4 is configured as follows
 *
 *     - Base address 0x38000000
 *     - 32 bit port size
 *     - Data error checking disabled
 *     - Read/Write access
 *     - SDRAM local bus
 *     - Not used for atomic operations
 *     - No data pipelining is done
 *     - Valid
 *
 */

#define CFG_BR4_PRELIM	((CFG_SDRAM2_BASE & BRx_BA_MSK) |\
			 BRx_PS_32			|\
			 BRx_DECC_NONE			|\
			 BRx_MS_SDRAM_L			|\
			 BRx_V)

/*
 * With 16MB SDRAM, OR4 is configured as follows
 *     - 4 internal banks per device
 *     - Row start address bit is A10 with LSDMR[PBI] = 0
 *     - 12 row address lines
 *     - Back-to-back page mode
 *     - Internal bank interleaving within save device enabled
 */

#define CFG_OR4_PRELIM	(MEG_TO_AM(CFG_SDRAM2_SIZE)	|\
			 ORxS_BPD_4			|\
			 ORxS_ROWST_PBI0_A10		|\
			 ORxS_NUMR_12)


/*-----------------------------------------------------------------------
 * LSDMR - Local Bus SDRAM Mode Register
 *     Ref: Section 10.3.4 on page 10-24
 *-----------------------------------------------------------------------
 */

/* With a 16 MB onboard SDRAM, the LSDMR is configured as follows:
 *
 *     - Page Based Interleaving,
 *     - Refresh Enable,
 *     - Normal Operation
 *     - Address Multiplexing where A5 is output on A13 pin
 *	 (A6 on A15, and so on),
 *     - use address pins A15-A17 as bank select,
 *     - A11 is output on SDA10 during an ACTIVATE command,
 *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 *	 is 2 clocks,
 *     - earliest timing for READ/WRITE command after ACTIVATE command is
 *	 2 clocks,
 *     - SDRAM burst length is 8
 *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 *     - External Address Multiplexing disabled
 *     - CAS Latency is 2.
 */
#define CFG_LSDMR	(PSDMR_RFEN	      |\
			 PSDMR_SDAM_A13_IS_A5 |\
			 PSDMR_BSMA_A15_A17   |\
			 PSDMR_SDA10_PBI0_A11 |\
			 PSDMR_RFRC_7_CLK     |\
			 PSDMR_PRETOACT_2W    |\
			 PSDMR_ACTTORW_2W     |\
			 PSDMR_BL	      |\
			 PSDMR_LDOTOPRE_1C    |\
			 PSDMR_WRC_1C	      |\
			 PSDMR_CL_2)

#define CFG_LSRT	0x0e

/*-----------------------------------------------------------------------
 * BR5 - Base Register
 *     Ref: Section 10.3.1 on page 10-14
 * OR5 - Option Register
 *     Ref: Section 10.3.2 on page 10-16
 *-----------------------------------------------------------------------
 */

/*
 * Bank 5 EEProm and Mailbox
 *
 * The EEPROM and mailbox live on the same chip select.
 * the eeprom is selected if the MSb of the address is set and the mailbox is
 * selected if the MSb of the address is clear.
 *
 */

/* BR5 is configured as follows:
 *
 *     - Base address of 0x32000000/0xF2000000
 *     - 8 bit
 *     - Data error checking disabled
 *     - Read/Write access
 *     - GPCM 60x Bus
 *     - SDRAM local bus
 *     - No data pipelining is done
 *     - Valid
 */

#define CFG_BR5_PRELIM	((CFG_MAILBOX_BASE & BRx_BA_MSK) |\
			 BRx_PS_8			 |\
			 BRx_DECC_NONE			 |\
			 BRx_MS_GPCM_P			 |\
			 BRx_V)
/* OR5 is configured as follows
 *     - buffer control enabled
 *     - chip select negated normally
 *     - CS output 1/2 clock after address
 *     - 15 wait states
 *     - *PSDVAL is generated internally by the memory controller
 *	 unless *GTA is asserted earlier externally.
 *     - Relaxed timing is generated by the GPCM for accesses
 *	 initiated to this memory region.
 *     - One idle clock is inserted between a read access from the
 *	 current bank and the next access.
 */

#define CFG_OR5_PRELIM ((P2SZ_TO_AM(CFG_MAILBOX_SIZE) & ~0x80000000) |\
			 ORxG_ACS_DIV2				     |\
			 ORxG_SCY_15_CLK			     |\
			 ORxG_TRLX				     |\
			 ORxG_EHTR)

/*-----------------------------------------------------------------------
 * BR6 - Base Register
 *     Ref: Section 10.3.1 on page 10-14
 * OR6 - Option Register
 *     Ref: Section 10.3.2 on page 10-18
 *-----------------------------------------------------------------------
 */

/* Bank 6 - I/O select
 *
 */

/* BR6 is configured as follows:
 *
 *     - Base address of 0xE0000000
 *     - 16 bit port size
 *     - Data errors checking is disabled
 *     - Read and write access
 *     - GPCM 60x bus
 *     - Access are handled by the memory controller according to MSEL
 *     - Not used for atomic operations
 *     - No data pipelining is done
 *     - Valid
 */
#define CFG_BR6_PRELIM	((CFG_IOSELECT_BASE & BRx_BA_MSK) |\
			   BRx_PS_16			  |\
			   BRx_MS_GPCM_P		  |\
			   BRx_V)

/* OR6 is configured as follows
 *     - buffer control enabled
 *     - chip select negated normally
 *     - CS output 1/2 clock after address
 *     - 15 wait states
 *     - *PSDVAL is generated internally by the memory controller
 *	 unless *GTA is asserted earlier externally.
 *     - Relaxed timing is generated by the GPCM for accesses
 *	 initiated to this memory region.
 *     - One idle clock is inserted between a read access from the
 *	 current bank and the next access.
 */

#define CFG_OR6_PRELIM (MEG_TO_AM(CFG_IOSELECT_SIZE) |\
			 ORxG_ACS_DIV2		     |\
			 ORxG_SCY_15_CLK	     |\
			 ORxG_TRLX		     |\
			 ORxG_EHTR)


/*-----------------------------------------------------------------------
 * BR7 - Base Register
 *     Ref: Section 10.3.1 on page 10-14
 * OR7 - Option Register
 *     Ref: Section 10.3.2 on page 10-18
 *-----------------------------------------------------------------------
 */

/* Bank 7 - LEDs and switches
 *
 *  LEDs     are at 0x00001 (write only)
 *  switches are at 0x00001 (read only)
 */
#ifdef CFG_LED_BASE

/* BR7 is configured as follows:
 *
 *     - Base address of 0xA0000000
 *     - 8 bit port size
 *     - Data errors checking is disabled
 *     - Read and write access
 *     - GPCM 60x bus
 *     - Access are handled by the memory controller according to MSEL
 *     - Not used for atomic operations
 *     - No data pipelining is done
 *     - Valid
 */
#define CFG_BR7_PRELIM	((CFG_LED_BASE & BRx_BA_MSK)	 |\
			   BRx_PS_8			 |\
			   BRx_DECC_NONE		 |\
			   BRx_MS_GPCM_P		 |\
			   BRx_V)

/* OR7 is configured as follows:
 *
 *     - 1 byte
 *     - *BCTL0 is asserted upon access to the current memory bank
 *     - *CW / *WE are negated a quarter of a clock earlier
 *     - *CS is output at the same time as the address lines
 *     - Uses a clock cycle length of 15
 *     - *PSDVAL is generated internally by the memory controller
 *	 unless *GTA is asserted earlier externally.
 *     - Relaxed timing is generated by the GPCM for accesses
 *	 initiated to this memory region.
 *     - One idle clock is inserted between a read access from the
 *	 current bank and the next access.
 */
#define CFG_OR7_PRELIM	(ORxG_AM_MSK		       |\
			 ORxG_CSNT		       |\
			 ORxG_ACS_DIV1		       |\
			 ORxG_SCY_15_CLK	       |\
			 ORxG_TRLX		       |\
			 ORxG_EHTR)
#endif /* CFG_LED_BASE */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM	0x02	/* Software reboot		     */

#endif	/* __CONFIG_H */