ads860.h

AT91RM9200的完整启动代码：包括loader, boot及U-boot三部分均已编译通过！欢迎下载使用！

/* the other CS:s are determined by looking at parameters in BCSRx */

#define BCSR_ADDR	   ((uint) 0xff010000)
#define BCSR_SIZE	   ((uint)(64 * 1024))

#define FLASH_BASE0_PRELIM  0xfe000000	/* FLASH bank #0    */
#define FLASH_BASE1_PRELIM  0x00000000	/* FLASH bank #1    */

#define CFG_REMAP_OR_AM	    0xff000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM    0xffe00000	/* OR addr mask */

/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0    */
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)

#ifdef USE_REAL_FLASH_VALUES
/*
 * These values fit our FADS860T ...
 * The "default" behaviour with 1Mbyte initial doesn't work for us!
 */
#define CFG_BR0_PRELIM	0x0fe000001	/* Real values for the board */
#define CFG_OR0_PRELIM	0x0ffe00d34
#define CFG_BR2_PRELIM	0x000000081
#define CFG_OR2_PRELIM	0x0ff000800
#else
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
#endif

/* BCSRx - Board Control and Status Registers */
/* #define CFG_OR1_REMAP    CFG_OR0_REMAP */
#define CFG_OR1_PRELIM	0xffff8110	/* 64Kbyte address space */
#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V )

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CFG_MAMR_PTA	    97	/* start with divider for 100 MHz   */

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
#define CFG_MPTPR_2BK_4K    MPTPR_PTP_DIV16	/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_4K    MPTPR_PTP_DIV32	/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit	    */
#define CFG_MPTPR_2BK_8K    MPTPR_PTP_DIV8	/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_8K    MPTPR_PTP_DIV16	/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
	     MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
	     MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
	     MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
	     MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)

#define CFG_MAMR	0x13a01114
/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01	    /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02	    /* Software reboot		*/


/* values according to the manual */
#define BCSR0	((uint) (BCSR_ADDR + 00))
#define BCSR1	((uint) (BCSR_ADDR + 0x04))
#define BCSR2	((uint) (BCSR_ADDR + 0x08))
#define BCSR3	((uint) (BCSR_ADDR + 0x0c))
#define BCSR4	((uint) (BCSR_ADDR + 0x10))


/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )


/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_IDE_8xx_DIRECT	1   /* PCMCIA interface required    */
#undef	CONFIG_IDE_LED		    /* LED   for ide supported	*/
#define CONFIG_IDE_RESET	1   /* reset for ide supported	*/

#define CFG_IDE_MAXBUS		1   /* max. 2 IDE busses	*/
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */

#define CFG_PIO_MODE		0   /* IDE interface in PIO Mode 0  */
#define CFG_PC_IDE_RESET	((ushort)0x0008)    /* PC 12	*/

/* #define CFG_ATA_BASE_ADDR	0xFE100000 */
#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O		*/
#define CFG_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
#define CFG_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers   */


/* (F)ADS bitvalues by Helmut Buchsbaum
 * see MPC8xxADS User's Manual for a proper description
 * of the following structures
 */

#define BCSR0_ERB	((uint)0x80000000)
#define BCSR0_IP	((uint)0x40000000)
#define BCSR0_BDIS	((uint)0x10000000)
#define BCSR0_BPS_MASK	((uint)0x0C000000)
#define BCSR0_ISB_MASK	((uint)0x01800000)
#define BCSR0_DBGC_MASK ((uint)0x00600000)
#define BCSR0_DBPC_MASK ((uint)0x00180000)
#define BCSR0_EBDF_MASK ((uint)0x00060000)

#define BCSR1_FLASH_EN		 ((uint)0x80000000)
#define BCSR1_DRAM_EN		 ((uint)0x40000000)
#define BCSR1_ETHEN		 ((uint)0x20000000)
#define BCSR1_IRDEN		 ((uint)0x10000000)
#define BCSR1_FLASH_CFG_EN	 ((uint)0x08000000)
#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
#define BCSR1_BCSR_EN		 ((uint)0x02000000)
#define BCSR1_RS232EN_1		 ((uint)0x01000000)
#define BCSR1_PCCEN		 ((uint)0x00800000)
#define BCSR1_PCCVCC0		 ((uint)0x00400000)
#define BCSR1_PCCVCCON		    BCSR1_PCCVCC0
#define BCSR1_PCCVPP_MASK	 ((uint)0x00300000)
#define BCSR1_DRAM_HALF_WORD	 ((uint)0x00080000)
#define BCSR1_RS232EN_2		 ((uint)0x00040000)
#define BCSR1_SDRAM_EN		 ((uint)0x00020000)
#define BCSR1_PCCVCC1		 ((uint)0x00010000)

#define BCSR2_FLASH_PD_MASK	 ((uint)0xF0000000)
#define BCSR2_DRAM_PD_MASK	 ((uint)0x07800000)
#define BCSR2_DRAM_PD_SHIFT	 (23)
#define BCSR2_EXTTOLI_MASK	 ((uint)0x00780000)
#define BCSR2_DBREVNR_MASK	 ((uint)0x00030000)

#define BCSR3_DBID_MASK		 ((ushort)0x3800)
#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
#define BCSR3_BREVNR0		 ((ushort)0x0080)
#define BCSR3_FLASH_PD_MASK	 ((ushort)0x0070)
#define BCSR3_BREVN1		 ((ushort)0x0008)
#define BCSR3_BREVN2_MASK	 ((ushort)0x0003)

#define BCSR4_ETHLOOP		 ((uint)0x80000000)
#define BCSR4_TFPLDL		 ((uint)0x40000000)
#define BCSR4_TPSQEL		 ((uint)0x20000000)
#define BCSR4_SIGNAL_LAMP	 ((uint)0x10000000)
#ifdef CONFIG_MPC823
#define BCSR4_USB_EN		 ((uint)0x08000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860SAR
#define BCSR4_UTOPIA_EN		 ((uint)0x08000000)
#endif /* CONFIG_MPC860SAR */
#ifdef CONFIG_MPC860T
#define BCSR4_FETH_EN		 ((uint)0x08000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_USB_SPEED		 ((uint)0x04000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHCFG0		 ((uint)0x04000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VCCO		 ((uint)0x02000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHFDE		 ((uint)0x02000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_ON		 ((uint)0x00800000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC823
#define BCSR4_VDO_EKT_CLK_EN	 ((uint)0x00400000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHCFG1		 ((uint)0x00400000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_RST		 ((uint)0x00200000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHRST		 ((uint)0x00200000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_MODEM_EN		 ((uint)0x00100000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC823
#define BCSR4_DATA_VOICE	 ((uint)0x00080000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC850
#define BCSR4_DATA_VOICE	 ((uint)0x00080000)
#endif /* CONFIG_MPC850 */

#define CONFIG_DRAM_50MHZ	1
#define CONFIG_SDRAM_50MHZ

#ifdef CONFIG_MPC860T
/* Interrupt level assignments.
 */
#define FEC_INTERRUPT	SIU_LEVEL1  /* FEC interrupt */
#endif /* CONFIG_MPC860T */

/* We don't use the 8259.
 */
#define NR_8259_INTS	0

/* Machine type
 */
#define _MACH_8xx (_MACH_ads)

#if 0
#define CONFIG_DISK_SPINUP_TIME 1000000
#endif
#undef CONFIG_DISK_SPINUP_TIME	/* usin