ads860.h

AT91RM9200的完整启动代码：包括loader, boot及U-boot三部分均已编译通过！欢迎下载使用！

/*
  * A collection of structures, addresses, and values associated with
  * the Motorola 860 ADS board.	 Copied from the MBX stuff.
  * Magnus Damm added defines for 8xxrom and extended bd_info.
  * Helmut Buchsbaum added bitvalues for BCSRx
  *
  * Copyright (c) 1998 Dan Malek ([e-mail])
  */

/* ------------------------------------------------------------------------- */

#ifndef _CONFIG_ADS860_H
#define _CONFIG_ADS860_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#include <mpc8xx_irq.h>

#define CONFIG_MPC860		1
#define CONFIG_ADS		1

#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1	    */
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		19200	/* console baudrate */
#define CONFIG_PCMCIA		1	/* To enable PCMCIA support */

#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address defaults */
#define CFG_I2C_SLAVE		0x7F

#define MPC8XX_XIN		32768	/* 32.768 kHz input frequency	*/
#define MPC8XX_FACT		0x5F6	/* Multiply by 1526 */
					/* MPC8XX_FACT * MPC8XX_XIN = 50 MHz */

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled	    */
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
#endif

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND			    \
    "bootp; "				    \
    "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	    \
    "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
    "bootm"

#define CONFIG_LOADS_ECHO	1   /* echo on for serial download  */
#undef	CFG_LOADS_BAUD_CHANGE	    /* don't allow baudrate change  */

#undef	CONFIG_WATCHDOG		    /* watchdog disabled	*/

#define CONFIG_BOOTP_MASK   (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)


#if 0					/* private command defs */
#define CONFIG_COMMANDS	    (CONFIG_CMD_DFL | CFG_CMD_I2C | \
			     CFG_CMD_IDE | CFG_CMD_PCMCIA)
#endif
					/* default command defs */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_CACHE)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>


/*
 * Miscellaneous configurable options
 */
#undef	CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT	    "=>"	/* Monitor Command Prompt   */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	    1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE	    256		/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE	    (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	    16		/* max number of command args	*/
#define CFG_BARGSIZE	    CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START   0x00100000	/* memtest works on */
#define CFG_MEMTEST_END	    0x00F00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR	    0x00100000

#define CFG_HZ		    1000	/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xfff00000
#define CFG_IMMR_SIZE		((uint)(64 * 1024))

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE	    0x00000000
#define CFG_SRAM_BASE	    0x00000000
#define CFG_FLASH_BASE	    0xfe000000
#define CFG_FLASH_SIZE	    ((uint)(8 * 1024 * 1024))	/* max 8Mbyte */

#define CFG_MONITOR_LEN	    (384 << 10) /* Reserve 384 kB for Monitor	*/
#define CFG_MONITOR_BASE    CFG_FLASH_BASE
#define CFG_MALLOC_LEN	    (384 << 10) /* Reserve 384 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	    */
#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)  */
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)  */

#undef	CFG_ENV_IS_IN_NVRAM
#undef	CFG_ENV_IS_IN_EEPROM
#define CFG_ENV_IS_IN_FLASH	1

#define CFG_ENV_OFFSET		0x00040000
#define CFG_ENV_SIZE		0x4000	/* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE	0x40000 /* see README - env sector total size	*/

/* the other CS:s are determined by looking at parameters in BCSRx */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE  16		/* For all MPC8xx CPUs		*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4		/* log base 2 of the above value    */
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control			11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
	     SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
#else
#define CFG_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SUMCR - SIU Module Configuration		    11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CFG_SIUMCR  (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control			11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR   (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control	11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR   (PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
 *-----------------------------------------------------------------------
 * set the PLL, the low-power modes and the reset control (15-29)
 */
#define CFG_PLPRCR  (((MPC8XX_FACT-1) << 20) |	\
		PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register	15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK   SCCR_EBDF11
#define CFG_SCCR    (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
		   SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \
		   SCCR_DFLCD000 | SCCR_DFALCD00)


 /*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER	    0

/* Because of the way the 860 starts up and assigns CS0 the
* entire address space, we have to set the memory controller
* differently.	Normally, you write the option register
* first, and then enable the chip select by writing the
* base register.  For CS0, you must write the base register
* first, followed by the option register.
*/

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */