📄 ep8260.h
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/* * (C) Copyright 2002 * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG * * This file is based on similar values for other boards found in other * U-Boot config files, and some that I found in the EP8260 manual. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA *//* * board/config.h - configuration options, board specific * * Note: my board is a "SBC 8260 H, V.1.1" * - 64M 60x Bus SDRAM * - 32M Local Bus SDRAM * - 16M Flash (4 x AM29DL323DB90WDI) * - 128k NVRAM with RTC */#ifndef __CONFIG_H#define __CONFIG_H/* What is the oscillator's (UX2) frequency in Hz? */#define CONFIG_8260_CLKIN (66 * 1000 * 1000)/*----------------------------------------------------------------------- * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual *----------------------------------------------------------------------- * What should MODCK_H be? It is dependent on the oscillator * frequency, MODCK[1-3], and desired CPM and core frequencies. * Here are some example values (all frequencies are in MHz): * * MODCK_H MODCK[1-3] Osc CPM Core * ------- ---------- --- --- ---- * 0x2 0x2 33 133 133 * 0x2 0x3 33 133 166 * 0x2 0x4 33 133 200 * 0x2 0x5 33 133 233 * 0x2 0x6 33 133 266 * * 0x5 0x5 66 133 133 * 0x5 0x6 66 133 166 * 0x5 0x7 66 133 200 * * 0x6 0x0 66 133 233 * 0x6 0x1 66 133 266 * 0x6 0x2 66 133 300 */#define CFG_SBC_MODCK_H 0x05/* Define this if you want to boot from 0x00000100. If you don't define * this, you will need to program the bootloader to 0xfff00000, and * get the hardware reset config words at 0xfe000000. The simplest * way to do that is to program the bootloader at both addresses. * It is suggested that you just let U-Boot live at 0x00000000. *//* #define CFG_SBC_BOOT_LOW 1 */ /* only for HRCW *//* #undef CFG_SBC_BOOT_LOW *//* The reset command will not work as expected if the reset address does * not point to the correct address. */#define CFG_RESET_ADDRESS 0xFFF00100/* What should the base address of the main FLASH be and how big is * it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk * The main FLASH is whichever is connected to *CS0. U-Boot expects * this to be the SIMM. */#define CFG_FLASH0_BASE 0xFF000000#define CFG_FLASH0_SIZE 16/* What should the base address of the secondary FLASH be and how big * is it (in Mbytes)? The secondary FLASH is whichever is connected * to *CS6. U-Boot expects this to be the on board FLASH. If you don't * want it enabled, don't define these constants. */#define CFG_FLASH1_BASE 0#define CFG_FLASH1_SIZE 0#undef CFG_FLASH1_BASE#undef CFG_FLASH1_SIZE/* What should be the base address of SDRAM DIMM (60x bus) and how big is * it (in Mbytes)?*/#define CFG_SDRAM0_BASE 0x00000000#define CFG_SDRAM0_SIZE 64/* define CFG_LSDRAM if you want to enable the 32M SDRAM on the * local bus (8260 local bus is NOT cacheable!)*//* #define CFG_LSDRAM */#undef CFG_LSDRAM#ifdef CFG_LSDRAM/* What should be the base address of SDRAM DIMM (local bus) and how big is * it (in Mbytes)?*/ #define CFG_SDRAM1_BASE 0x04000000 #define CFG_SDRAM1_SIZE 32#else #define CFG_SDRAM1_BASE 0 #define CFG_SDRAM1_SIZE 0 #undef CFG_SDRAM1_BASE #undef CFG_SDRAM1_SIZE#endif /* CFG_LSDRAM *//* What should be the base address of NVRAM and how big is * it (in Bytes) */#define CFG_NVRAM_BASE_ADDR 0xFa080000#define CFG_NVRAM_SIZE (128*1024)-16/* The RTC is a Dallas DS1556 */#define CONFIG_RTC_DS1556/* What should be the base address of the LEDs and switch S0? * If you don't want them enabled, don't define this. */#define CFG_LED_BASE 0x00000000#undef CFG_LED_BASE/* * select serial console configuration * * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 * for SCC). * * if CONFIG_CONS_NONE is defined, then the serial console routines must * defined elsewhere. */#define CONFIG_CONS_ON_SMC /* define if console on SMC */#undef CONFIG_CONS_ON_SCC /* define if console on SCC */#undef CONFIG_CONS_NONE /* define if console on neither */#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console *//* * select ethernet configuration * * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be * defined elsewhere (as for the console), or CFG_CMD_NET must be removed * from CONFIG_COMMANDS to remove support for networking. */#undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */#define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */#undef CONFIG_ETHER_NONE /* define if ethernet on neither */#define CONFIG_ETHER_INDEX 3 /* which SCC/FCC channel for ethernet */#if ( CONFIG_ETHER_INDEX == 3 )/* * - Rx-CLK is CLK15 * - Tx-CLK is CLK16 * - RAM for BD/Buffers is on the local Bus (see 28-13) * - Enable Half Duplex in FSMR */# define CFG_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)/* * - RAM for BD/Buffers is on the local Bus (see 28-13) */#ifdef CFG_LSDRAM #define CFG_CPMFCR_RAMTYPE 3#else /* CFG_LSDRAM */ #define CFG_CPMFCR_RAMTYPE 0#endif /* CFG_LSDRAM *//* - Enable Half Duplex in FSMR *//* # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) */# define CFG_FCC_PSMR 0#else /* CONFIG_ETHER_INDEX */# error "on EP8260 ethernet must be FCC3"#endif /* CONFIG_ETHER_INDEX *//* * select i2c support configuration * * Supported configurations are {none, software, hardware} drivers. * If the software driver is chosen, there are some additional * configuration items that the driver uses to drive the port pins. */#undef CONFIG_HARD_I2C /* I2C with hardware support */#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */#define CFG_I2C_SLAVE 0x7F/* * Software (bit-bang) I2C driver configuration */#ifdef CONFIG_SOFT_I2C#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */#define I2C_ACTIVE (iop->pdir |= 0x00010000)#define I2C_TRISTATE (iop->pdir &= ~0x00010000)#define I2C_READ ((iop->pdat & 0x00010000) != 0)#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ else iop->pdat &= ~0x00010000#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ else iop->pdat &= ~0x00020000#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */#endif /* CONFIG_SOFT_I2C *//* #define CONFIG_RTC_DS174x *//* Define this to reserve an entire FLASH sector (256 KB) for * environment variables. Otherwise, the environment will be * put in the same sector as U-Boot, and changing variables * will erase U-Boot temporarily */#define CFG_ENV_IN_OWN_SECT/* Define to allow the user to overwrite serial and ethaddr */#define CONFIG_ENV_OVERWRITE/* What should the console's baud rate be? *//* #define CONFIG_BAUDRATE 57600 */#define CONFIG_BAUDRATE 115200/* Ethernet MAC address */#define CONFIG_ETHADDR 00:10:EC:00:30:8C#define CONFIG_IPADDR 192.168.254.130#define CONFIG_SERVERIP 192.168.254.49/* Set to a positive value to delay for running BOOTCOMMAND */#define CONFIG_BOOTDELAY -1/* undef this to save memory */#define CFG_LONGHELP/* Monitor Command Prompt */#define CFG_PROMPT "=> "/* Define this variable to enable the "hush" shell (from Busybox) as command line interpreter, thus enabling powerful command line syntax like if...then...else...fi conditionals or `&&' and '||' constructs ("shell scripts"). If undefined, you get the old, much simpler behaviour with a somewhat smapper memory footprint.*/#define CFG_HUSH_PARSER#define CFG_PROMPT_HUSH_PS2 "> "/* What U-Boot subsytems do you want enabled? *//**/#define CONFIG_COMMANDS ( CFG_CMD_ALL & \ ~CFG_CMD_BMP & \ ~CFG_CMD_BSP & \ ~CFG_CMD_DCR & \ ~CFG_CMD_DHCP & \ ~CFG_CMD_DOC & \ ~CFG_CMD_EEPROM & \ ~CFG_CMD_FDC & \ ~CFG_CMD_FDOS & \ ~CFG_CMD_HWFLOW & \ ~CFG_CMD_IDE & \ ~CFG_CMD_JFFS2 & \ ~CFG_CMD_KGDB & \ ~CFG_CMD_MII & \ ~CFG_CMD_MMC & \ ~CFG_CMD_NAND & \ ~CFG_CMD_PCI & \ ~CFG_CMD_PCMCIA & \ ~CFG_CMD_SCSI & \ ~CFG_CMD_SPI & \ ~CFG_CMD_USB & \ ~CFG_CMD_VFD & \ ~CFG_CMD_DTT )/* Where do the internal registers live? */#define CFG_IMMR 0xF0000000#define CFG_DEFAULT_IMMR 0x00010000/* Where do the on board registers (CS4) live? */#define CFG_REGS_BASE 0xFA000000/***************************************************************************** * * You should not have to modify any of the following settings * *****************************************************************************/#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */#define CONFIG_EP8260 11 /* on an Embedded Planet EP8260 Board, Rev. 11 */#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init *//* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */#include <cmd_confdefs.h>/* * Miscellaneous configurable options */#if (CONFIG_COMMANDS & CFG_CMD_KGDB)# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */#else# define CFG_CBSIZE 256 /* Console I/O Buffer Size */#endif/* Print Buffer Size */#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)#define CFG_MAXARGS 8 /* max number of command args */#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */#ifdef CFG_LSDRAM #define CFG_MEMTEST_START 0x04000000 /* memtest works on */ #define CFG_MEMTEST_END 0x06000000 /* 64-96 MB in SDRAM */#else #define CFG_MEMTEST_START 0x00000000 /* memtest works on */ #define CFG_MEMTEST_END 0x02000000 /* 0-32 MB in SDRAM */#endif /* CFG_LSDRAM */#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */#define CFG_LOAD_ADDR 0x00100000 /* default load address */#define CFG_TFTP_LOADADDR 0x00100000 /* default load address for network file downloads */#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks *//* valid baudrates */
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