cpc45.h

AT91RM9200的完整启动代码：包括loader, boot及U-boot三部分均已编译通过！欢迎下载使用！

/*
 * (C) Copyright 2001-2003
 * Wolfgang Denk, DENX Software Engineering, [e-mail].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 *
 * Configuration settings for the CPC45 board.
 *
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X		1
#define CONFIG_MPC8245		1
#define CONFIG_CPC45		1


#define CONFIG_CONS_INDEX	1
#define CONFIG_BAUDRATE		9600
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz	*/

#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"

#define CONFIG_BOOTDELAY	5

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)

#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
				CFG_CMD_BEDBUG  | \
				CFG_CMD_DHCP	| \
				CFG_CMD_PCI	| \
				0 /* CFG_CMD_DATE */	)

/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
 */
#include <cmd_confdefs.h>


/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/

#if 1
#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
#endif
#ifdef	CFG_HUSH_PARSER
#define	CFG_PROMPT_HUSH_PS2	"> "
#endif

/* Print Buffer Size
 */
#define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)

#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
#define CFG_LOAD_ADDR	0x00100000	/* Default load address		*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */

#define CFG_SDRAM_BASE	    0x00000000

#if defined(CONFIG_BOOT_ROM)
#define CFG_FLASH_BASE	    0xFF000000
#else
#define CFG_FLASH_BASE	    0xFF800000
#endif

#define CFG_RESET_ADDRESS   0xFFF00100

#define CFG_EUMB_ADDR	    0xFCE00000

#define CFG_MONITOR_BASE    TEXT_BASE

#define CFG_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/

#define CFG_MEMTEST_START   0x00004000	/* memtest works on		*/
#define CFG_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/

	/* Maximum amount of RAM.
	 */
#define CFG_MAX_RAM_SIZE    0x10000000


#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
#undef CFG_RAMBOOT
#else
#define CFG_RAMBOOT
#endif


/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */

	/* Size in bytes reserved for initial data
	 */
#define CFG_GBL_DATA_SIZE    128

#define CFG_INIT_RAM_ADDR     0x40000000
#define CFG_INIT_RAM_END      0x1000
#define CFG_GBL_DATA_OFFSET  (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)

/*
 * NS16550 Configuration
 */
#define CFG_NS16550
#define CFG_NS16550_SERIAL

#define CFG_NS16550_REG_SIZE	1

#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_NS16550_COM1	(CFG_EUMB_ADDR + 0x4500)
#define CFG_NS16550_COM2	(CFG_EUMB_ADDR + 0x4600)
#define	DUART_DCR		(CFG_EUMB_ADDR + 0x4511)

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8240 user's manual.
 */

#define CONFIG_SYS_CLK_FREQ  33000000
#define CFG_HZ		     1000
/*
 * SDRAM Configuration Settings
 * Please note: currently only 64 and 128 MB SDRAM size supported
 * set CFG_SDRAM_SIZE to 64 or 128
 * Memory configuration using SPD information stored on the SODIMMs
 * not yet supported.
 */

#define	CFG_SDRAM_SIZE    64		/* SDRAM size -- 64 or 128 MB supported */

	/* Bit-field values for MCCR1.
	 */
#define CFG_ROMNAL	    0
#define CFG_ROMFAL	    7

#if (CFG_SDRAM_SIZE == 64)			/* 64 MB */
#define CFG_BANK0_ROW	0			/* SDRAM bank 7-0 row address */
#elif (CFG_SDRAM_SIZE == 128)			/* 128 MB */
#define CFG_BANK0_ROW	2			/* SDRAM bank 7-0 row address */
#else
#  error "SDRAM size not supported"
#endif
#define CFG_BANK1_ROW	0
#define CFG_BANK2_ROW	0
#define CFG_BANK3_ROW	0
#define CFG_BANK4_ROW	0
#define CFG_BANK5_ROW	0
#define CFG_BANK6_ROW	0
#define CFG_BANK7_ROW	0

	/* Bit-field values for MCCR2.
	 */
#define CFG_REFINT	    430	    /* Refresh interval			*/

	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
	 */
#define CFG_BSTOPRE	    192

	/* Bit-field values for MCCR3.
	 */
#define CFG_REFREC	    2	    /* Refresh to activate interval	*/
#define CFG_RDLAT	    3	    /* Data latancy from read command	*/

	/* Bit-field values for MCCR4.
	 */
#define CFG_PRETOACT	    2	    /* Precharge to activate interval	*/
#define CFG_ACTTOPRE	    5	    /* Activate to Precharge interval	*/
#define CFG_SDMODE_CAS_LAT  2	    /* SDMODE CAS latancy		*/
#define CFG_SDMODE_WRAP	    0	    /* SDMODE wrap type			*/
#define CFG_SDMODE_BURSTLEN 2	    /* SDMODE Burst length		*/
#define CFG_ACTORW	    2
#define CFG_REGISTERD_TYPE_BUFFER 1
#define CFG_EXTROM	    1
#define CFG_REGDIMM	    0

/* Memory bank settings.
 * Only bits 20-29 are actually used from these vales to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end