svm_sc8xx.h

AT91RM9200的完整启动代码：包括loader, boot及U-boot三部分均已编译通过！欢迎下载使用！

/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
#define CFG_HWINFO_MAGIC	0x46454C38	/* 'SVM8' */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
/*#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
*/
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR 0xffffff88
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef	CONFIG_CAN_DRIVER
/*#define CFG_SIUMCR 0x00610c00	*/
#define CFG_SIUMCR 0x00000000	
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	0x0001

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CFG_RTCSC	0x00c3

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	0x0000

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 */
#if defined (CONFIG_100MHz)
#define CFG_PLPRCR 0x06301000
#define CONFIG_8xx_GCLK_FREQ 100000000
#elif defined (CONFIG_80MHz)
#define CFG_PLPRCR 0x04f01000
#define CONFIG_8xx_GCLK_FREQ 80000000
#elif defined(CONFIG_75MHz)	
#define CFG_PLPRCR 0x04a00100	
#define CONFIG_8xx_GCLK_FREQ 75000000
#elif defined(CONFIG_66MHz)	
#define CFG_PLPRCR 0x04101000	
#define CONFIG_8xx_GCLK_FREQ 66000000
#elif defined(CONFIG_50MHz)	
#define CFG_PLPRCR 0x03101000	
#define CONFIG_8xx_GCLK_FREQ 50000000
#endif	

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#ifdef	CONFIG_BUS_DIV2	
#define CFG_SCCR	0x02020000 | SCCR_RTSEL
#else			/* up to 50 MHz we use a 1:1 clock */
#define CFG_SCCR    0x02000000 | SCCR_RTSEL
#endif	

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#undef	CONFIG_IDE_8xx_PCCARD   	/* Use IDE with PC Card	Adapter	*/

#define	CONFIG_IDE_8xx_DIRECT	1	/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1 	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_BASE_ADDR       0xFE100010
#define CFG_ATA_IDE0_OFFSET     0x0000
/*#define CFG_ATA_IDE1_OFFSET     0x0C00 */
#define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O
					   */
#define CFG_ATA_REG_OFFSET      0x0200  /* Offset for normal register accesses
					   */
#define CFG_ATA_ALT_OFFSET      0x0210  /* Offset for alternate registers
					   */
#define CONFIG_ATAPI    
#define CFG_PIO_MODE 0

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CFG_DER	0x2002000F*/
#define CFG_DER	0x0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing:
 */
#if defined(CONFIG_100MHz) 
#define CFG_OR_TIMING_FLASH 0x000002f4	
#define CFG_OR_TIMING_DOC   0x000002f4	
#define CFG_MxMR_PTx 0x61000000
#define CFG_MPTPR 0x400

#elif  defined(CONFIG_80MHz)
#define CFG_OR_TIMING_FLASH 0x00000ff4	
#define CFG_OR_TIMING_DOC   0x000001f4	
#define CFG_MxMR_PTx 0x4e000000
#define CFG_MPTPR 0x400

#elif defined(CONFIG_75MHz) 
#define CFG_OR_TIMING_FLASH 0x000008f4	
#define CFG_OR_TIMING_DOC   0x000002f4	
#define CFG_MxMR_PTx 0x49000000
#define CFG_MPTPR 0x400

#elif defined(CONFIG_66MHz)
#define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
        OR_SCY_3_CLK | OR_EHTR | OR_BI)
/*#define CFG_OR_TIMING_FLASH 0x000001f4 */
#define CFG_OR_TIMING_DOC   0x000003f4	
#define CFG_MxMR_PTx  0x40000000
#define CFG_MPTPR 0x400

#else		/*   50 MHz */
#define CFG_OR_TIMING_FLASH 0x00000ff4
#define CFG_OR_TIMING_DOC   0x000001f4	
#define CFG_MxMR_PTx  0x30000000
#define CFG_MPTPR 0x400
#endif	/*CONFIG_??MHz */


#if  defined (CONFIG_BOOT_8B)   /* 512K X 8 ,29F040 , 2MB space */
#define CFG_OR0_PRELIM	(0xffe00000 | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)
#elif  defined (CONFIG_BOOT_16B)   /* 29lv160 X 16 , 4MB space */
#define CFG_OR0_PRELIM	(0xffc00000 | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
#elif defined( CONFIG_BOOT_32B )  /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */
#define CFG_OR0_PRELIM	(0xfc000000 | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
#else
#error Boot device port size missing.
#endif

/*
 * Disk-On-Chip configuration
 */

#define CFG_DOC_SHORT_TIMEOUT
#define CFG_MAX_DOC_DEVICE      1       /* Max number of DOC devices    */

#define CFG_DOC_SUPPORT_2000
#define CFG_DOC_SUPPORT_MILLENNIUM
#define CFG_DOC_BASE 0x80000000


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */