gw8260.h

AT91RM9200的完整启动代码：包括loader, boot及U-boot三部分均已编译通过！欢迎下载使用！

/*
 * (C) Copyright 2000
 * Murray Jensen <[e-mail]>
 *
 * (C) Copyright 2000
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <[e-mail]>
 *
 * (C) Copyright 2001
 * Advent Networks, Inc. <http://www.adventnetworks.com>
 * Jay Monkman <[e-mail]>
 *
 * (C) Copyright 2001
 * Advent Networks, Inc. <http://www.adventnetworks.com>
 * Oliver Brown <[e-mail]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*********************************************************************/
/* DESCRIPTION:
 *   This file contains the board configuartion for the GW8260 board.
 *
 * MODULE DEPENDENCY:
 *   None
 *
 * RESTRICTIONS/LIMITATIONS:
 *   None
 *
 * Copyright (c) 2001, Advent Networks, Inc.
 */
/*********************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/* Enable debug prints */
#undef DEBUG                  /* General debug */
#undef DEBUG_BOOTP_EXT        /* Debug received vendor fields */

/* What is the oscillator's (UX2) frequency in Hz? */
#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)

/*-----------------------------------------------------------------------
 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
 *-----------------------------------------------------------------------
 * What should MODCK_H be? It is dependent on the oscillator
 * frequency, MODCK[1-3], and desired CPM and core frequencies.
 * Here are some example values (all frequencies are in MHz):
 *
 * MODCK_H   MODCK[1-3]  Osc    CPM    Core  S2-6   S2-7   S2-8
 * -------   ----------  ---    ---    ----  -----  -----  -----
 * 0x5       0x5     66 133     133    Open  Close  Open
 * 0x5       0x6     66 133     166    Open  Open   Close
 * 0x5       0x7     66 133     200    Open  Open   Open
 * 0x6       0x0     66 133     233    Close Close  Close
 * 0x6       0x1     66 133     266    Close Close  Open
 * 0x6       0x2     66 133     300    Close Open   Close
 */
#define CFG_SBC_MODCK_H 0x05

/* Define this if you want to boot from 0x00000100. If you don't define
 * this, you will need to program the bootloader to 0xfff00000, and
 * get the hardware reset config words at 0xfe000000. The simplest
 * way to do that is to program the bootloader at both addresses.
 * It is suggested that you just let U-Boot live at 0x00000000.
 */
#define CFG_SBC_BOOT_LOW 1

/* What should the base address of the main FLASH be and how big is
 * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
 * The main FLASH is whichever is connected to *CS0. U-Boot expects
 * this to be the SIMM.
 */
#define CFG_FLASH0_BASE 0x40000000
#define CFG_FLASH0_SIZE 8

/* Define CFG_FLASH_CHECKSUM to enable flash checksum during boot.
 * Note: the 'flashchecksum' environment variable must also be set to 'y'.
 */
#define CFG_FLASH_CHECKSUM

/* What should be the base address of SDRAM DIMM and how big is
 * it (in Mbytes)?
 */
#define CFG_SDRAM0_BASE 0x00000000
#define CFG_SDRAM0_SIZE 64

/*
 * DRAM tests
 *   CFG_DRAM_TEST - enables the following tests.
 *
 *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
 *                        Environment variable 'test_dram_data' must be
 *                        set to 'y'.
 *   CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
 *                        addressable. Environment variable
 *                        'test_dram_address' must be set to 'y'.
 *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
 *                        This test takes about 6 minutes to test 64 MB.
 *                        Environment variable 'test_dram_walk' must be
 *                        set to 'y'.
 */
#define CFG_DRAM_TEST
#if defined(CFG_DRAM_TEST)
#define CFG_DRAM_TEST_DATA
#define CFG_DRAM_TEST_ADDRESS
#define CFG_DRAM_TEST_WALK
#endif /* CFG_DRAM_TEST */

/*
 * GW8260 with 16 MB DIMM:
 *
 *     0x0000 0000     Exception Vector code, 8k
 *           :
 *     0x0000 1FFF
 *     0x0000 2000     Free for Application Use
 *           :
 *           :
 *
 *           :
 *           :
 *     0x00F5 FF30     Monitor Stack (Growing downward)
 *                     Monitor Stack Buffer (0x80)
 *     0x00F5 FFB0     Board Info Data
 *     0x00F6 0000     Malloc Arena
 *           :          CFG_ENV_SECT_SIZE, 256k
 *           :          CFG_MALLOC_LEN,    128k
 *     0x00FC 0000     RAM Copy of Monitor Code
 *           :              CFG_MONITOR_LEN,   256k
 *     0x00FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
 */

/*
 * GW8260 with 64 MB DIMM:
 *
 *     0x0000 0000     Exception Vector code, 8k
 *           :
 *     0x0000 1FFF
 *     0x0000 2000     Free for Application Use
 *           :
 *           :
 *
 *           :
 *           :
 *     0x03F5 FF30     Monitor Stack (Growing downward)
 *                     Monitor Stack Buffer (0x80)
 *     0x03F5 FFB0     Board Info Data
 *     0x03F6 0000     Malloc Arena
 *           :          CFG_ENV_SECT_SIZE, 256k
 *           :          CFG_MALLOC_LEN,    128k
 *     0x03FC 0000     RAM Copy of Monitor Code
 *           :              CFG_MONITOR_LEN,   256k
 *     0x03FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
 */


/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere.
 */
#define CONFIG_CONS_ON_SMC  1   /* define if console on SMC */
#undef  CONFIG_CONS_ON_SCC      /* define if console on SCC */
#undef  CONFIG_CONS_NONE        /* define if console on neither */
#define CONFIG_CONS_INDEX   1   /* which SMC/SCC channel for console */

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 * from CONFIG_COMMANDS to remove support for networking.
 */

#undef  CONFIG_ETHER_ON_SCC
#define CONFIG_ETHER_ON_FCC
#undef  CONFIG_ETHER_NONE       /* define if ethernet on neither */

#ifdef  CONFIG_ETHER_ON_SCC
#define CONFIG_ETHER_INDEX  1   /* which SCC/FCC channel for ethernet */
#endif  /* CONFIG_ETHER_ON_SCC */

#ifdef  CONFIG_ETHER_ON_FCC
#define CONFIG_ETHER_INDEX  2   /* which SCC/FCC channel for ethernet */
#define CONFIG_MII              /* MII PHY management           */
#define CONFIG_BITBANGMII       /* bit-bang MII PHY management  */
/*
 * Port pins used for bit-banged MII communictions (if applicable).
 */
#define MDIO_PORT   2       /* Port C */
#define MDIO_ACTIVE    (iop->pdir |=  0x00400000)
#define MDIO_TRISTATE  (iop->pdir &= ~0x00400000)
#define MDIO_READ     ((iop->pdat &  0x00400000) != 0)

#define MDIO(bit)   if(bit) iop->pdat |=  0x00400000; \
            else            iop->pdat &= ~0x00400000

#define MDC(bit)    if(bit) iop->pdat |=  0x00200000; \
            else    iop->pdat &= ~0x00200000

#define MIIDELAY    udelay(1)
#endif  /* CONFIG_ETHER_ON_FCC */

#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)

/*
 * - Rx-CLK is CLK13
 * - Tx-CLK is CLK14
 * - Select bus for bd/buffers (see 28-13)
 * - Enable Full Duplex in FSMR
 */
# define CFG_CMXFCR_MASK	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
# define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
# define CFG_CPMFCR_RAMTYPE	0
# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)

#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)

/*
 * - Rx-CLK is CLK15
 * - Tx-CLK is CLK16
 * - Select bus for bd/buffers (see 28-13)
 * - Enable Full Duplex in FSMR
 */
# define CFG_CMXFCR_MASK	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
# define CFG_CMXFCR_VALUE	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
# define CFG_CPMFCR_RAMTYPE	0
# define CFG_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)

#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */

/* Define this to reserve an entire FLASH sector (256 KB) for
 * environment variables. Otherwise, the environment will be
 * put in the same sector as U-Boot, and changing variables
 * will erase U-Boot temporarily
 */
#define CFG_ENV_IN_OWN_SECT

/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* What should the console's baud rate be? */
#define CONFIG_BAUDRATE     115200

/* Ethernet MAC address - This is set to all zeros to force an
 *                        an error if we use BOOTP without setting
 *                        the MAC address
 */
#define CONFIG_ETHADDR      00:00:00:00:00:00

/* Set to a positive value to delay for running BOOTCOMMAND */
#define CONFIG_BOOTDELAY    5   /* autoboot after 5 seconds */

/* Be selective on what keys can delay or stop the autoboot process
 *     To stop  use: " "
 */
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT  "Autobooting in %d seconds, press \" \" to stop\n"
#define CONFIG_AUTOBOOT_STOP_STR    " "
#undef  CONFIG_AUTOBOOT_DELAY_STR
#define DEBUG_BOOTKEYS      0

/* Add support for a few extra bootp options like:
 *  - File size
 *  - DNS
 */
#define CONFIG_BOOTP_MASK   (CONFIG_BOOTP_DEFAULT | \
                             CONFIG_BOOTP_BOOTFILESIZE | \
                             CONFIG_BOOTP_DNS)

/* undef this to save memory */
#define CFG_LONGHELP

/* Monitor Command Prompt */
#define CFG_PROMPT      "=> "

/* What U-Boot subsytems do you want enabled? */
#define CONFIG_COMMANDS     (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
                               CFG_CMD_BEDBUG  | \
                               CFG_CMD_ELF | \
                               CFG_CMD_ASKENV  | \
                               CFG_CMD_ECHO    | \
                               CFG_CMD_REGINFO | \
                               CFG_CMD_IMMAP   | \
                               CFG_CMD_MII)

/* Where do the internal registers live? */
#define CFG_IMMR        0xf0000000

/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef  CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/* What is the address of IO controller */
#define CFG_IO_BASE 0xe0000000

/*****************************************************************************
 *
 * You should not have to modify any of the following settings
 *
 *****************************************************************************/

#define CONFIG_MPC8260      1   /* This is an MPC8260 CPU   */
#define CONFIG_GW8260       1   /* on an GW8260 Board  */

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#  define CFG_CBSIZE        1024    /* Console I/O Buffer Size       */
#else
#  define CFG_CBSIZE        256     /* Console I/O Buffer Size       */
#endif

/* Print Buffer Size */
#define CFG_PBSIZE    (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)

#define CFG_MAXARGS     8          /* max number of command args   */

#define CFG_BARGSIZE    CFG_CBSIZE /* Boot Argument Buffer Size    */

/* Convert clocks to MHZ when passing board info to kernel.
 * This must be defined for eariler 2.4 kernels (~2.4.4).
 */
#define CONFIG_CLOCKS_IN_MHZ

#define CFG_LOAD_ADDR   0x100000 /* default load address */
#define CFG_HZ          1000     /* decrementer freq: 1 ms ticks */


/* memtest works from the end of the exception vector table
 * to the end of the DRAM less monitor and malloc area
 */
#define CFG_MEMTEST_START   0x2000

#define CFG_STACK_USAGE     0x10000 /* Reserve 64k for the stack usage */

#define CFG_MEM_END_USAGE   ( CFG_MONITOR_LEN \
                            + CFG_MALLOC_LEN \
                            + CFG_ENV_SECT_SIZE \
                            + CFG_STACK_USAGE )

#define CFG_MEMTEST_END     ( CFG_SDRAM_SIZE * 1024 * 1024 \
                            - CFG_MEM_END_USAGE )

/* valid baudrates */
#define CFG_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CFG_FLASH_BASE  CFG_FLASH0_BASE
#define CFG_FLASH_SIZE  CFG_FLASH0_SIZE
#define CFG_SDRAM_BASE  CFG_SDRAM0_BASE
#define CFG_SDRAM_SIZE  CFG_SDRAM0_SIZE

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 */
#if defined(CFG_SBC_BOOT_LOW)
#  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
#else
#  define  CFG_SBC_HRCW_BOOT_FLAGS  (0)
#endif /* defined(CFG_SBC_BOOT_LOW) */

/* get the HRCW ISB field from CFG_IMMR */
#define CFG_SBC_HRCW_IMMR   ( ((CFG_IMMR & 0x10000000) >> 10) | \
                  ((CFG_IMMR & 0x01000000) >>  7) | \
                  ((CFG_IMMR & 0x00100000) >>  4) )

#define CFG_HRCW_MASTER     ( HRCW_BPS11                | \
                  HRCW_DPPC11               | \
                  CFG_SBC_HRCW_IMMR         | \
                  HRCW_MMR00                | \
                  HRCW_LBPC11               | \
                  HRCW_APPC10               | \
                  HRCW_CS10PC00             | \