📄 scm.h
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#endif/*----------------------------------------------------------------------- * HIDx - Hardware Implementation-dependent Registers 2-11 *----------------------------------------------------------------------- * HID0 also contains cache control - initially enable both caches and * invalidate contents, then the final state leaves only the instruction * cache enabled. Note that Power-On and Hard reset invalidate the caches, * but Soft reset does not. * * HID1 has only read-only information - nothing to set. */#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ HID0_IFEM|HID0_ABE)#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)#define CFG_HID2 0/*----------------------------------------------------------------------- * RMR - Reset Mode Register 5-5 *----------------------------------------------------------------------- * turn on Checkstop Reset Enable */#define CFG_RMR RMR_CSRE/*----------------------------------------------------------------------- * BCR - Bus Configuration 4-25 *----------------------------------------------------------------------- */#ifdef CONFIG_BUSMODE_60x#define CFG_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */#else#define BCR_APD01 0x10000000#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */#endif/*----------------------------------------------------------------------- * SIUMCR - SIU Module Configuration 4-31 *----------------------------------------------------------------------- */#if 0#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)#else#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10)#endif/*----------------------------------------------------------------------- * SYPCR - System Protection Control 4-35 * SYPCR can only be written once after reset! *----------------------------------------------------------------------- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable */#if defined(CONFIG_WATCHDOG)#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)#else#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ SYPCR_SWRI|SYPCR_SWP)#endif /* CONFIG_WATCHDOG *//*----------------------------------------------------------------------- * TMCNTSC - Time Counter Status and Control 4-40 *----------------------------------------------------------------------- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, * and enable Time Counter */#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)/*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 4-42 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable * Periodic timer */#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)/*----------------------------------------------------------------------- * SCCR - System Clock Control 9-8 *----------------------------------------------------------------------- * Ensure DFBRG is Divide by 16 */#define CFG_SCCR 0/*----------------------------------------------------------------------- * RCCR - RISC Controller Configuration 13-7 *----------------------------------------------------------------------- */#define CFG_RCCR 0/* * Init Memory Controller: * * Bank Bus Machine PortSz Device * ---- --- ------- ------ ------ * 0 60x GPCM 64 bit FLASH * 1 60x SDRAM 64 bit SDRAM * 2 Local SDRAM 32 bit SDRAM * */ /* Initialize SDRAM on local bus */#define CFG_INIT_LOCAL_SDRAM#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB *//* Minimum mask to separate preliminary * address ranges for CS[0:2] */#define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */#define CFG_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */#define CFG_MPTPR 0x4000/*----------------------------------------------------------------------------- * Address for Mode Register Set (MRS) command *----------------------------------------------------------------------------- * In fact, the address is rather configuration data presented to the SDRAM on * its address lines. Because the address lines may be mux'ed externally either * for 8 column or 9 column devices, some bits appear twice in the 8260's * address: * * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | *----------------------------------------------------------------------------- */#define CFG_MRS_OFFS 0x00000110/* Bank 0 - FLASH */#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ BRx_PS_64 |\ BRx_MS_GPCM_P |\ BRx_V)#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ ORxG_CSNT |\ ORxG_ACS_DIV1 |\ ORxG_SCY_3_CLK |\ ORxG_EHTR |\ ORxG_TRLX) /* SDRAM on TQM8260 can have either 8 or 9 columns. * The number affects configuration values. *//* Bank 1 - 60x bus SDRAM */#define CFG_PSRT 0x20#define CFG_LSRT 0x20#ifndef CFG_RAMBOOT#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ BRx_PS_64 |\ BRx_MS_SDRAM_P |\ BRx_V)#define CFG_OR1_PRELIM CFG_OR1_8COL /* SDRAM initialization values for 8-column chips */#define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ ORxS_BPD_4 |\ ORxS_ROWST_PBI1_A7 |\ ORxS_NUMR_12)#define CFG_PSDMR_8COL (PSDMR_PBI |\ PSDMR_SDAM_A15_IS_A5 |\ PSDMR_BSMA_A12_A14 |\ PSDMR_SDA10_PBI1_A8 |\ PSDMR_RFRC_7_CLK |\ PSDMR_PRETOACT_2W |\ PSDMR_ACTTORW_2W |\ PSDMR_LDOTOPRE_1C |\ PSDMR_WRC_2C |\ PSDMR_EAMUX |\ PSDMR_CL_2) /* SDRAM initialization values for 9-column chips */#define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ ORxS_BPD_4 |\ ORxS_ROWST_PBI1_A5 |\ ORxS_NUMR_13)#define CFG_PSDMR_9COL (PSDMR_PBI |\ PSDMR_SDAM_A16_IS_A5 |\ PSDMR_BSMA_A12_A14 |\ PSDMR_SDA10_PBI1_A7 |\ PSDMR_RFRC_7_CLK |\ PSDMR_PRETOACT_2W |\ PSDMR_ACTTORW_2W |\ PSDMR_LDOTOPRE_1C |\ PSDMR_WRC_2C |\ PSDMR_EAMUX |\ PSDMR_CL_2)/* Bank 2 - Local bus SDRAM */#ifdef CFG_INIT_LOCAL_SDRAM#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ BRx_PS_32 |\ BRx_MS_SDRAM_L |\ BRx_V)#define CFG_OR2_PRELIM CFG_OR2_8COL#define SDRAM_BASE2_PRELIM 0x80000000 /* SDRAM initialization values for 8-column chips */#define CFG_OR2_8COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ ORxS_BPD_4 |\ ORxS_ROWST_PBI1_A8 |\ ORxS_NUMR_12)#define CFG_LSDMR_8COL (PSDMR_PBI |\ PSDMR_SDAM_A15_IS_A5 |\ PSDMR_BSMA_A13_A15 |\ PSDMR_SDA10_PBI1_A9 |\ PSDMR_RFRC_7_CLK |\ PSDMR_PRETOACT_2W |\ PSDMR_ACTTORW_2W |\ PSDMR_BL |\ PSDMR_LDOTOPRE_1C |\ PSDMR_WRC_2C |\ PSDMR_CL_2) /* SDRAM initialization values for 9-column chips */#define CFG_OR2_9COL ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ ORxS_BPD_4 |\ ORxS_ROWST_PBI1_A6 |\ ORxS_NUMR_13)#define CFG_LSDMR_9COL (PSDMR_PBI |\ PSDMR_SDAM_A16_IS_A5 |\ PSDMR_BSMA_A13_A15 |\ PSDMR_SDA10_PBI1_A8 |\ PSDMR_RFRC_7_CLK |\ PSDMR_PRETOACT_2W |\ PSDMR_ACTTORW_2W |\ PSDMR_BL |\ PSDMR_LDOTOPRE_1C |\ PSDMR_WRC_2C |\ PSDMR_CL_2)#endif /* CFG_INIT_LOCAL_SDRAM */#endif /* CFG_RAMBOOT */#define CFG_CAN0_BASE 0xc0000000#define CFG_CAN1_BASE 0xc0008000#define CFG_FIOX_BASE 0xc0010000#define CFG_FDOHM_BASE 0xc0018000#define CFG_EXTPROM_BASE 0xc2000000#define CFG_CAN_SIZE 0x00000100#define CFG_FIOX_SIZE 0x00000020#define CFG_FDOHM_SIZE 0x00002000#define CFG_EXTPROM_BANK_SIZE 0x01000000#define EXT_EEPROM_MAX_FLASH_BANKS 0x02/* CS3 - CAN 0 */#define CFG_CAN0_BR3 ((CFG_CAN0_BASE & BRx_BA_MSK) |\ BRx_PS_8 |\ BRx_MS_UPMA |\ BRx_V)#define CFG_CAN0_OR3 (P2SZ_TO_AM(CFG_CAN_SIZE) |\ ORxU_BI |\ ORxU_EHTR_4IDLE)/* CS4 - CAN 1 */#define CFG_CAN1_BR4 ((CFG_CAN1_BASE & BRx_BA_MSK) |\ BRx_PS_8 |\ BRx_MS_UPMA |\ BRx_V)#define CFG_CAN1_OR4 (P2SZ_TO_AM(CFG_CAN_SIZE) |\ ORxU_BI |\ ORxU_EHTR_4IDLE)/* CS5 - Extended PROM (16MB optional) */#define CFG_EXTPROM_BR5 ((CFG_EXTPROM_BASE & BRx_BA_MSK)|\ BRx_PS_32 |\ BRx_MS_GPCM_P |\ BRx_V)#define CFG_EXTPROM_OR5 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\ ORxG_CSNT |\ ORxG_ACS_DIV4 |\ ORxG_SCY_5_CLK |\ ORxG_TRLX)/* CS6 - Extended PROM (16MB optional) */#define CFG_EXTPROM_BR6 (((CFG_EXTPROM_BASE + \ CFG_EXTPROM_BANK_SIZE) & BRx_BA_MSK)|\ BRx_PS_32 |\ BRx_MS_GPCM_P |\ BRx_V)#define CFG_EXTPROM_OR6 (P2SZ_TO_AM(CFG_EXTPROM_BANK_SIZE)|\ ORxG_CSNT |\ ORxG_ACS_DIV4 |\ ORxG_SCY_5_CLK |\ ORxG_TRLX)/* CS7 - FPGA FIOX: Glue Logic */#define CFG_FIOX_BR7 ((CFG_FIOX_BASE & BRx_BA_MSK) |\ BRx_PS_32 |\ BRx_MS_GPCM_P |\ BRx_V)#define CFG_FIOX_OR7 (P2SZ_TO_AM(CFG_FIOX_SIZE) |\ ORxG_ACS_DIV4 |\ ORxG_SCY_5_CLK |\ ORxG_TRLX)/* CS8 - FPGA DOH Master */#define CFG_FDOHM_BR8 ((CFG_FDOHM_BASE & BRx_BA_MSK) |\ BRx_PS_16 |\ BRx_MS_GPCM_P |\ BRx_V)#define CFG_FDOHM_OR8 (P2SZ_TO_AM(CFG_FDOHM_SIZE) |\ ORxG_ACS_DIV4 |\ ORxG_SCY_5_CLK |\ ORxG_TRLX)/* FPGA configuration */#define CFG_PD_FIOX_PROG (1 << (31- 5)) /* PD 5 */#define CFG_PD_FIOX_DONE (1 << (31-28)) /* PD 28 */#define CFG_PD_FIOX_INIT (1 << (31-29)) /* PD 29 */#define CFG_PD_FDOHM_PROG (1 << (31- 4)) /* PD 4 */#define CFG_PD_FDOHM_DONE (1 << (31-26)) /* PD 26 */#define CFG_PD_FDOHM_INIT (1 << (31-27)) /* PD 27 */#endif /* __CONFIG_H */⌨️ 快捷键说明
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