📄 mipsregs.h
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extern __inline__ unsigned int \set_cp0_##name(unsigned int set) \{ \ unsigned int res; \ \ res = read_32bit_cp0_register(register); \ res |= set; \ write_32bit_cp0_register(register, res); \ \ return res; \} \ \extern __inline__ unsigned int \clear_cp0_##name(unsigned int clear) \{ \ unsigned int res; \ \ res = read_32bit_cp0_register(register); \ res &= ~clear; \ write_32bit_cp0_register(register, res); \ \ return res; \} \ \extern __inline__ unsigned int \change_cp0_##name(unsigned int change, unsigned int new) \{ \ unsigned int res; \ \ res = read_32bit_cp0_register(register); \ res &= ~change; \ res |= (new & change); \ if(change) \ write_32bit_cp0_register(register, res); \ \ return res; \}__BUILD_SET_CP0(status,CP0_STATUS)__BUILD_SET_CP0(cause,CP0_CAUSE)__BUILD_SET_CP0(config,CP0_CONFIG)#endif /* defined (_LANGUAGE_ASSEMBLY) *//* * Bitfields in the R4xx0 cp0 status register */#define ST0_IE 0x00000001#define ST0_EXL 0x00000002#define ST0_ERL 0x00000004#define ST0_KSU 0x00000018# define KSU_USER 0x00000010# define KSU_SUPERVISOR 0x00000008# define KSU_KERNEL 0x00000000#define ST0_UX 0x00000020#define ST0_SX 0x00000040#define ST0_KX 0x00000080#define ST0_DE 0x00010000#define ST0_CE 0x00020000/* * Bitfields in the R[23]000 cp0 status register. */#define ST0_IEC 0x00000001#define ST0_KUC 0x00000002#define ST0_IEP 0x00000004#define ST0_KUP 0x00000008#define ST0_IEO 0x00000010#define ST0_KUO 0x00000020/* bits 6 & 7 are reserved on R[23]000 */#define ST0_ISC 0x00010000#define ST0_SWC 0x00020000#define ST0_CM 0x00080000/* * Bits specific to the R4640/R4650 */#define ST0_UM (1 << 4)#define ST0_IL (1 << 23)#define ST0_DL (1 << 24)/* * Bitfields in the TX39 family CP0 Configuration Register 3 */#define TX39_CONF_ICS_SHIFT 19#define TX39_CONF_ICS_MASK 0x00380000#define TX39_CONF_ICS_1KB 0x00000000#define TX39_CONF_ICS_2KB 0x00080000#define TX39_CONF_ICS_4KB 0x00100000#define TX39_CONF_ICS_8KB 0x00180000#define TX39_CONF_ICS_16KB 0x00200000#define TX39_CONF_DCS_SHIFT 16#define TX39_CONF_DCS_MASK 0x00070000#define TX39_CONF_DCS_1KB 0x00000000#define TX39_CONF_DCS_2KB 0x00010000#define TX39_CONF_DCS_4KB 0x00020000#define TX39_CONF_DCS_8KB 0x00030000#define TX39_CONF_DCS_16KB 0x00040000#define TX39_CONF_CWFON 0x00004000#define TX39_CONF_WBON 0x00002000#define TX39_CONF_RF_SHIFT 10#define TX39_CONF_RF_MASK 0x00000c00#define TX39_CONF_DOZE 0x00000200#define TX39_CONF_HALT 0x00000100#define TX39_CONF_LOCK 0x00000080#define TX39_CONF_ICE 0x00000020#define TX39_CONF_DCE 0x00000010#define TX39_CONF_IRSIZE_SHIFT 2#define TX39_CONF_IRSIZE_MASK 0x0000000c#define TX39_CONF_DRSIZE_SHIFT 0#define TX39_CONF_DRSIZE_MASK 0x00000003/* * Status register bits available in all MIPS CPUs. */#define ST0_IM 0x0000ff00#define STATUSB_IP0 8#define STATUSF_IP0 (1 << 8)#define STATUSB_IP1 9#define STATUSF_IP1 (1 << 9)#define STATUSB_IP2 10#define STATUSF_IP2 (1 << 10)#define STATUSB_IP3 11#define STATUSF_IP3 (1 << 11)#define STATUSB_IP4 12#define STATUSF_IP4 (1 << 12)#define STATUSB_IP5 13#define STATUSF_IP5 (1 << 13)#define STATUSB_IP6 14#define STATUSF_IP6 (1 << 14)#define STATUSB_IP7 15#define STATUSF_IP7 (1 << 15)#define STATUSB_IP8 0#define STATUSF_IP8 (1 << 0)#define STATUSB_IP9 1#define STATUSF_IP9 (1 << 1)#define STATUSB_IP10 2#define STATUSF_IP10 (1 << 2)#define STATUSB_IP11 3#define STATUSF_IP11 (1 << 3)#define STATUSB_IP12 4#define STATUSF_IP12 (1 << 4)#define STATUSB_IP13 5#define STATUSF_IP13 (1 << 5)#define STATUSB_IP14 6#define STATUSF_IP14 (1 << 6)#define STATUSB_IP15 7#define STATUSF_IP15 (1 << 7)#define ST0_CH 0x00040000#define ST0_SR 0x00100000#define ST0_BEV 0x00400000#define ST0_RE 0x02000000#define ST0_FR 0x04000000#define ST0_CU 0xf0000000#define ST0_CU0 0x10000000#define ST0_CU1 0x20000000#define ST0_CU2 0x40000000#define ST0_CU3 0x80000000#define ST0_XX 0x80000000 /* MIPS IV naming *//* * Bitfields and bit numbers in the coprocessor 0 cause register. * * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. */#define CAUSEB_EXCCODE 2#define CAUSEF_EXCCODE (31 << 2)#define CAUSEB_IP 8#define CAUSEF_IP (255 << 8)#define CAUSEB_IP0 8#define CAUSEF_IP0 (1 << 8)#define CAUSEB_IP1 9#define CAUSEF_IP1 (1 << 9)#define CAUSEB_IP2 10#define CAUSEF_IP2 (1 << 10)#define CAUSEB_IP3 11#define CAUSEF_IP3 (1 << 11)#define CAUSEB_IP4 12#define CAUSEF_IP4 (1 << 12)#define CAUSEB_IP5 13#define CAUSEF_IP5 (1 << 13)#define CAUSEB_IP6 14#define CAUSEF_IP6 (1 << 14)#define CAUSEB_IP7 15#define CAUSEF_IP7 (1 << 15)#define CAUSEB_IV 23#define CAUSEF_IV (1 << 23)#define CAUSEB_CE 28#define CAUSEF_CE (3 << 28)#define CAUSEB_BD 31#define CAUSEF_BD (1 << 31)/* * Bits in the coprozessor 0 config register. */#define CONF_CM_CACHABLE_NO_WA 0#define CONF_CM_CACHABLE_WA 1#define CONF_CM_UNCACHED 2#define CONF_CM_CACHABLE_NONCOHERENT 3#define CONF_CM_CACHABLE_CE 4#define CONF_CM_CACHABLE_COW 5#define CONF_CM_CACHABLE_CUW 6#define CONF_CM_CACHABLE_ACCELERATED 7#define CONF_CM_CMASK 7#define CONF_DB (1 << 4)#define CONF_IB (1 << 5)#define CONF_SC (1 << 17)#define CONF_AC (1 << 23)#define CONF_HALT (1 << 25)/* * R10000 performance counter definitions. * * FIXME: The R10000 performance counter opens a nice way to implement CPU * time accounting with a precission of one cycle. I don't have * R10000 silicon but just a manual, so ... *//* * Events counted by counter #0 */#define CE0_CYCLES 0#define CE0_INSN_ISSUED 1#define CE0_LPSC_ISSUED 2#define CE0_S_ISSUED 3#define CE0_SC_ISSUED 4#define CE0_SC_FAILED 5#define CE0_BRANCH_DECODED 6#define CE0_QW_WB_SECONDARY 7#define CE0_CORRECTED_ECC_ERRORS 8#define CE0_ICACHE_MISSES 9#define CE0_SCACHE_I_MISSES 10#define CE0_SCACHE_I_WAY_MISSPREDICTED 11#define CE0_EXT_INTERVENTIONS_REQ 12#define CE0_EXT_INVALIDATE_REQ 13#define CE0_VIRTUAL_COHERENCY_COND 14#define CE0_INSN_GRADUATED 15/* * Events counted by counter #1 */#define CE1_CYCLES 0#define CE1_INSN_GRADUATED 1#define CE1_LPSC_GRADUATED 2#define CE1_S_GRADUATED 3#define CE1_SC_GRADUATED 4#define CE1_FP_INSN_GRADUATED 5#define CE1_QW_WB_PRIMARY 6#define CE1_TLB_REFILL 7#define CE1_BRANCH_MISSPREDICTED 8#define CE1_DCACHE_MISS 9#define CE1_SCACHE_D_MISSES 10#define CE1_SCACHE_D_WAY_MISSPREDICTED 11#define CE1_EXT_INTERVENTION_HITS 12#define CE1_EXT_INVALIDATE_REQ 13#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15/* * These flags define in which priviledge mode the counters count events */#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */#endif /* _ASM_MIPSREGS_H */⌨️ 快捷键说明
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