inca-ip.h

AT91RM9200的完整启动代码：包括loader, boot及U-boot三部分均已编译通过！欢迎下载使用！

      
/***DSP Control Register***/ 
#define INCA_IP_MBC_DCTRL                        ((volatile u32*)(INCA_IP_MBC+ 0x00A0))
#define INCA_IP_MBC_DCTRL_BA                              (1 << 0)
#define INCA_IP_MBC_DCTRL_BMOD (value)               (((( 1 << 3) - 1) & (value)) << 1)
#define INCA_IP_MBC_DCTRL_IDL                              (1 << 4)
#define INCA_IP_MBC_DCTRL_RES                              (1 << 15)
      
/***DSP Status Register***/ 
#define INCA_IP_MBC_DSTA                         ((volatile u32*)(INCA_IP_MBC+ 0x00A4))
#define INCA_IP_MBC_DSTA_IDLE                            (1 << 0)
#define INCA_IP_MBC_DSTA_PD                              (1 << 1)
      
/***DSP Test 1 Register***/ 
#define INCA_IP_MBC_DTST1                        ((volatile u32*)(INCA_IP_MBC+ 0x00A8))
#define INCA_IP_MBC_DTST1_ABORT                          (1 << 0)
#define INCA_IP_MBC_DTST1_HWF32                          (1 << 1)
#define INCA_IP_MBC_DTST1_HWF4M                          (1 << 2)
#define INCA_IP_MBC_DTST1_HWFOP                          (1 << 3)		
         
/***********************************************************************/
/*  Module      :  Switch register address and bits                    */
/***********************************************************************/
         
#define INCA_IP_Switch                       (0xBF104000)
/***********************************************************************/   

      
/***Unknown Destination Register***/ 
#define INCA_IP_Switch_UN_DEST                      ((volatile u32*)(INCA_IP_Switch+ 0x0000))
#define INCA_IP_Switch_UN_DEST_CB                              (1 << 8)
#define INCA_IP_Switch_UN_DEST_LB                              (1 << 7)
#define INCA_IP_Switch_UN_DEST_PB                              (1 << 6)
#define INCA_IP_Switch_UN_DEST_CM                              (1 << 5)
#define INCA_IP_Switch_UN_DEST_LM                              (1 << 4)
#define INCA_IP_Switch_UN_DEST_PM                              (1 << 3)
#define INCA_IP_Switch_UN_DEST_CU                              (1 << 2)
#define INCA_IP_Switch_UN_DEST_LU                              (1 << 1)
#define INCA_IP_Switch_UN_DEST_PU                              (1 << 0)
      
/***VLAN Control Register***/ 
#define INCA_IP_Switch_VLAN_CTRL                    ((volatile u32*)(INCA_IP_Switch+ 0x0004))
#define INCA_IP_Switch_VLAN_CTRL_SC                              (1 << 6)
#define INCA_IP_Switch_VLAN_CTRL_SL                              (1 << 5)
#define INCA_IP_Switch_VLAN_CTRL_SP                              (1 << 4)
#define INCA_IP_Switch_VLAN_CTRL_TC                              (1 << 3)
#define INCA_IP_Switch_VLAN_CTRL_TL                              (1 << 2)
#define INCA_IP_Switch_VLAN_CTRL_TP                              (1 << 1)
#define INCA_IP_Switch_VLAN_CTRL_VA                              (1 << 0)
      
/***PC VLAN Configuration Register***/ 
#define INCA_IP_Switch_PC_VLAN                      ((volatile u32*)(INCA_IP_Switch+ 0x0008))
#define INCA_IP_Switch_PC_VLAN_PRI (value)                (((( 1 << 3) - 1) & (value)) << 12)
#define INCA_IP_Switch_PC_VLAN_VLAN_ID (value)            (((( 1 << 12) - 1) & (value)) << 0)
      
/***LAN VLAN Configuration Register***/ 
#define INCA_IP_Switch_LAN_VLAN                    ((volatile u32*)(INCA_IP_Switch+ 0x000C))
#define INCA_IP_Switch_LAN_VLAN_PRI (value)                (((( 1 << 3) - 1) & (value)) << 12)
#define INCA_IP_Switch_LAN_VLAN_VLAN_ID (value)            (((( 1 << 12) - 1) & (value)) << 0)
      
/***CPU VLAN Configuration Register***/ 
#define INCA_IP_Switch_CPU_VLAN                    ((volatile u32*)(INCA_IP_Switch+ 0x0010))
#define INCA_IP_Switch_CPU_VLAN_PRI (value)                (((( 1 << 3) - 1) & (value)) << 12)
#define INCA_IP_Switch_CPU_VLAN_VLAN_ID (value)            (((( 1 << 12) - 1) & (value)) << 0)
      
/***Priority CoS Mapping Register***/ 
#define INCA_IP_Switch_PRI_CoS                      ((volatile u32*)(INCA_IP_Switch+ 0x0014))
#define INCA_IP_Switch_PRI_CoS_P7                              (1 << 7)
#define INCA_IP_Switch_PRI_CoS_P6                              (1 << 6)
#define INCA_IP_Switch_PRI_CoS_P5                              (1 << 5)
#define INCA_IP_Switch_PRI_CoS_P4                              (1 << 4)
#define INCA_IP_Switch_PRI_CoS_P3                              (1 << 3)
#define INCA_IP_Switch_PRI_CoS_P2                              (1 << 2)
#define INCA_IP_Switch_PRI_CoS_P1                              (1 << 1)
#define INCA_IP_Switch_PRI_CoS_P0                              (1 << 0)
      
/***Spanning Tree Port Status Register***/ 
#define INCA_IP_Switch_ST_PT                        ((volatile u32*)(INCA_IP_Switch+ 0x0018))
#define INCA_IP_Switch_ST_PT_CPS (value)                (((( 1 << 2) - 1) & (value)) << 4)
#define INCA_IP_Switch_ST_PT_LPS (value)                (((( 1 << 2) - 1) & (value)) << 2)
#define INCA_IP_Switch_ST_PT_PPS (value)                (((( 1 << 2) - 1) & (value)) << 0)
      
/***ARL Control Register***/ 
#define INCA_IP_Switch_ARL_CTL                      ((volatile u32*)(INCA_IP_Switch+ 0x001C))
#define INCA_IP_Switch_ARL_CTL_CHCC                            (1 << 15)
#define INCA_IP_Switch_ARL_CTL_CHCL                            (1 << 14)
#define INCA_IP_Switch_ARL_CTL_CHCP                            (1 << 13)
#define INCA_IP_Switch_ARL_CTL_CC                              (1 << 12)
#define INCA_IP_Switch_ARL_CTL_CL                              (1 << 11)
#define INCA_IP_Switch_ARL_CTL_CP                              (1 << 10)
#define INCA_IP_Switch_ARL_CTL_CG                              (1 << 9)
#define INCA_IP_Switch_ARL_CTL_PS                              (1 << 8)
#define INCA_IP_Switch_ARL_CTL_MRO                              (1 << 7)
#define INCA_IP_Switch_ARL_CTL_SRC                              (1 << 6)
#define INCA_IP_Switch_ARL_CTL_ATS                              (1 << 5)
#define INCA_IP_Switch_ARL_CTL_AGE_TICK_SEL (value)       (((( 1 << 3) - 1) & (value)) << 2)
#define INCA_IP_Switch_ARL_CTL_MAF                              (1 << 1)
#define INCA_IP_Switch_ARL_CTL_ENL                              (1 << 0)
#define INCA_IP_Switch_ARL_CTL_Res (value)                (((( 1 << 19) - 1) & (value)) << 13)
      
/***CPU Access Control Register***/ 
#define INCA_IP_Switch_CPU_ACTL                    ((volatile u32*)(INCA_IP_Switch+ 0x0020))
#define INCA_IP_Switch_CPU_ACTL_RA                              (1 << 31)
#define INCA_IP_Switch_CPU_ACTL_RW                              (1 << 30)
#define INCA_IP_Switch_CPU_ACTL_Res (value)                (((( 1 << 21) - 1) & (value)) << 9)
#define INCA_IP_Switch_CPU_ACTL_AVA                              (1 << 8)
#define INCA_IP_Switch_CPU_ACTL_IDX (value)                (((( 1 << 8) - 1) & (value)) << 0)
      
/***CPU Access Data Register 1***/ 
#define INCA_IP_Switch_DATA1                        ((volatile u32*)(INCA_IP_Switch+ 0x0024))
#define INCA_IP_Switch_DATA1_Data (value)               (((( 1 << 24) - 1) & (value)) << 0)
      
/***CPU Access Data Register 2***/ 
#define INCA_IP_Switch_DATA2                        ((volatile u32*)(INCA_IP_Switch+ 0x0028))
#define INCA_IP_Switch_DATA2_Data
      
/***CPU Port Control Register***/ 
#define INCA_IP_Switch_CPU_PCTL                    ((volatile u32*)(INCA_IP_Switch+ 0x002C))
#define INCA_IP_Switch_CPU_PCTL_DA_PORTS (value)          (((( 1 << 3) - 1) & (value)) << 11)
#define INCA_IP_Switch_CPU_PCTL_DAC                              (1 << 10)
#define INCA_IP_Switch_CPU_PCTL_MA_STATE (value)          (((( 1 << 3) - 1) & (value)) << 7)
#define INCA_IP_Switch_CPU_PCTL_MAM                              (1 << 6)
#define INCA_IP_Switch_CPU_PCTL_MA_Ports (value)          (((( 1 << 3) - 1) & (value)) << 3)
#define INCA_IP_Switch_CPU_PCTL_MAC                              (1 << 2)
#define INCA_IP_Switch_CPU_PCTL_EML                              (1 << 1)
#define INCA_IP_Switch_CPU_PCTL_EDL                              (1 << 0)
#define INCA_IP_Switch_CPU_PCTL_Res (value)                (((( 1 << 18) - 1) & (value)) << 14)
      
/***DSCP CoS Mapping Register 1***/ 
#define INCA_IP_Switch_DSCP_COS1                    ((volatile u32*)(INCA_IP_Switch+ 0x0030))
#define INCA_IP_Switch_DSCP_COS1_DSCP
      
/***DSCP CoS Mapping Register 1***/ 
#define INCA_IP_Switch_DSCP_COS2                    ((volatile u32*)(INCA_IP_Switch+ 0x0034))
#define INCA_IP_Switch_DSCP_COS2_DSCP
      
/***PC WFQ Control Register***/ 
#define INCA_IP_Switch_PC_WFQ_CTL                   ((volatile u32*)(INCA_IP_Switch+ 0x0080))
#define INCA_IP_Switch_PC_WFQ_CTL_P1                              (1 << 9)
#define INCA_IP_Switch_PC_WFQ_CTL_P0                              (1 << 8)
#define INCA_IP_Switch_PC_WFQ_CTL_WT1 (value)                (((( 1 << 3) - 1) & (value)) << 5)
#define INCA_IP_Switch_PC_WFQ_CTL_WT0 (value)                (((( 1 << 3) - 1) & (value)) << 2)
#define INCA_IP_Switch_PC_WFQ_CTL_SCH_SEL (value)            (((( 1 << 2) - 1) & (value)) << 0)
      
/***PC TX Control Register***/ 
#define INCA_IP_Switch_PC_TX_CTL                    ((volatile u32*)(INCA_IP_Switch+ 0x0084))
#define INCA_IP_Switch_PC_TX_CTL_ELR                              (1 << 1)
#define INCA_IP_Switch_PC_TX_CTL_EER                              (1 << 0)
      
/***LAN WFQ Control Register***/ 
#define INCA_IP_Switch_LAN_WFQ_CTL                  ((volatile u32*)(INCA_IP_Switch+ 0x0100))
#define INCA_IP_Switch_LAN_WFQ_CTL_P1                              (1 << 9)
#define INCA_IP_Switch_LAN_WFQ_CTL_P0                              (1 << 8)
#define INCA_IP_Switch_LAN_WFQ_CTL_WT1 (value)                (((( 1 << 3) - 1) & (value)) << 5)
#define INCA_IP_Switch_LAN_WFQ_CTL_WT0 (value)                (((( 1 << 3) - 1) & (value)) << 2)
#define INCA_IP_Switch_LAN_WFQ_CTL_SCH_SEL (value)            (((( 1 << 2) - 1) & (value)) << 0)
      
/***LAN TX Control Register***/ 
#define INCA_IP_Switch_LAN_TX_CTL                   ((volatile u32*)(INCA_IP_Switch+ 0x0104))
#define INCA_IP_Switch_LAN_TX_CTL_ELR                              (1 << 1)
#define INCA_IP_Switch_LAN_TX_CTL_EER                              (1 << 0)
      
/***CPU WFQ Control Register***/ 
#define INCA_IP_Switch_CPU_WFQ_CTL                  ((volatile u32*)(INCA_IP_Switch+ 0x0180))
#define INCA_IP_Switch_CPU_WFQ_CTL_P1                              (1 << 9)
#define INCA_IP_Switch_CPU_WFQ_CTL_P0                              (1 << 8)
#define INCA_IP_Switch_CPU_WFQ_CTL_WT1 (value)                (((( 1 << 3) - 1) & (value)) << 5)
#define INCA_IP_Switch_CPU_WFQ_CTL_WT0 (value)                (((( 1 << 3) - 1) & (value)) << 2)
#define INCA_IP_Switch_CPU_WFQ_CTL_SCH_SEL (value)            (((( 1 << 2) - 1) & (value)) << 0)
      
/***PM PC RX Watermark Register***/ 
#define INCA_IP_Switch_PC_WM                        ((volatile u32*)(INCA_IP_Switch+ 0x0200))
#define INCA_IP_Switch_PC_WM_RX_WM1 (value)             (((( 1 << 8) - 1) & (value)) << 24)
#define INCA_IP_Switch_PC_WM_RX_WM2 (value)             (((( 1 << 8) - 1) & (value)) << 16)
#define INCA_IP_Switch_PC_WM_RX_WM3 (value)             (((( 1 << 8) - 1) & (value)) << 8)
#define INCA_IP_Switch_PC_WM_RX_WM4 (value)             (((( 1 << 8) - 1) & (value)) << 0)
      
/***PM LAN RX Watermark Register***/ 
#define INCA_IP_Switch_LAN_WM                       ((volatile u32*)(INCA_IP_Switch+ 0x0204))
#define INCA_IP_Switch_LAN_WM_RX_WM1 (value)             (((( 1 << 8) - 1) & (value)) << 24)
#define INCA_IP_Switch_LAN_WM_RX_WM2 (value)             (((( 1 << 8) - 1) & (value)) << 16)
#define INCA_IP_Switch_LAN_WM_RX_WM3 (value)             (((( 1 << 8) - 1) & (value)) << 8)
#define INCA_IP_Switch_LAN_WM_RX_WM4 (value)             (((( 1 << 8) - 1) & (value)) << 0)
      
/***PM CPU RX Watermark Register***/ 
#define INCA_IP_Switch_CPU_WM                       ((volatile u32*)(INCA_IP_Switch+ 0x0208))
#define INCA_IP_Switch_CPU_WM_RX_WM1 (value)             (((( 1 << 8) - 1) & (value)) << 24)
#define INCA_IP_Switch_CPU_WM_RX_WM2 (value)             (((( 1 << 8) - 1) & (value)) << 16)
#define INCA_IP_Switch_CPU_WM_RX_WM3 (value)             (((( 1 << 8) - 1) & (value)) << 8)
#define INCA_IP_Switch_CPU_WM_RX_WM4 (value)             (((( 1 << 8) - 1) & (value)) << 0)
      
/***PM CPU RX Watermark Register***/ 
#define INCA_IP_Switch_GBL_WM                       ((volatile u32*)(INCA_IP_Switch+ 0x020C))
#define INCA_IP_Switch_GBL_WM_GBL_RX_WM1 (value)         (((( 1 << 8) - 1) & (value)) << 24)
#define INCA_IP_Switch_GBL_WM_GBL_RX_WM2 (value)         (((( 1 << 8) - 1) & (value)) << 16)
#define INCA_IP_Switch_GBL_WM_GBL_RX_WM3 (value)         (((( 1 << 8) - 1) & (value)) << 8)
#define INCA_IP_Switch_GBL_WM_GBL_RX_WM4 (value)         (((( 1 << 8) - 1) & (value)) << 0)
      
/***PM Control Register***/ 
#define INCA_IP_Switch_PM_CTL                       ((volatile u32*)(INCA_IP_Switch+ 0x0210))
#define INCA_IP_Switch_PM_CTL_GDN                              (1 << 3)
#define INCA_IP_Switch_PM_CTL_CDN                              (1 << 2)
#define INCA_IP_Switch_PM_CTL_LDN                              (1 << 1)
#define INCA_IP_Switch_PM_CTL_PDN                              (1 << 0)
      
/***PM Header Control Register***/ 
#define INCA_IP_Switch_PMAC_HD_CTL                  ((volatile u32*)(INCA_IP_Switch+ 0x0280))
#define INCA_IP_Switch_PMAC_HD_CTL_RL2                              (1 << 21)
#define INCA_IP_Switch_PMAC_HD_CTL_RC                              (1 << 20)
#define INCA_IP_Switch_PMAC_HD_CTL_CM                              (1 << 19)
#define INCA_IP_Switch_PMAC_HD_CTL_CV                              (1 << 18)
#define INCA_IP_Switch_PMAC_HD_CTL_TYPE_LEN (value)          (((( 1 << 16) - 1) & (value)) << 2)
#define INCA_IP_Switch_PMAC_HD_CTL_TAG                              (1 << 1)