📄 inca-ip.h
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/****************************************************************************** Copyright (c) 2002, Infineon Technologies. All rights reserved. No Warranty Because the program is licensed free of charge, there is no warranty for the program, to the extent permitted by applicable law. Except when otherwise stated in writing the copyright holders and/or other parties provide the program "as is" without warranty of any kind, either expressed or implied, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The entire risk as to the quality and performance of the program is with you. should the program prove defective, you assume the cost of all necessary servicing, repair or correction. In no event unless required by applicable law or agreed to in writing will any copyright holder, or any other party who may modify and/or redistribute the program as permitted above, be liable to you for damages, including any general, special, incidental or consequential damages arising out of the use or inability to use the program (including but not limited to loss of data or data being rendered inaccurate or losses sustained by you or third parties or a failure of the program to operate with any other programs), even if such holder or other party has been advised of the possibility of such damages. ******************************************************************************/ /***********************************************************************//* Module : WDT register address and bits *//***********************************************************************/ #define INCA_IP_WDT (0xB8000000)/***********************************************************************/ /***Reset Status Register Power On***/ #define INCA_IP_WDT_RST_SR ((volatile u32*)(INCA_IP_WDT+ 0x0014)) /***Reset Request Register***/ #define INCA_IP_WDT_RST_REQ ((volatile u32*)(INCA_IP_WDT+ 0x0010))#define INCA_IP_WDT_RST_REQ_SWBOOT (1 << 24)#define INCA_IP_WDT_RST_REQ_SWCFG (1 << 16)#define INCA_IP_WDT_RST_REQ_RRPHY (1 << 5)#define INCA_IP_WDT_RST_REQ_RRHSP (1 << 4)#define INCA_IP_WDT_RST_REQ_RRFPI (1 << 3)#define INCA_IP_WDT_RST_REQ_RREXT (1 << 2)#define INCA_IP_WDT_RST_REQ_RRDSP (1 << 1)#define INCA_IP_WDT_RST_REQ_RRCPU (1 << 0) /***NMI Status Register***/ #define INCA_IP_WDT_NMISR ((volatile u32*)(INCA_IP_WDT+ 0x002C))#define INCA_IP_WDT_NMISR_NMIWDT (1 << 2)#define INCA_IP_WDT_NMISR_NMIPLL (1 << 1)#define INCA_IP_WDT_NMISR_NMIEXT (1 << 0) /***Manufacturer Identification Register***/ #define INCA_IP_WDT_MANID ((volatile u32*)(INCA_IP_WDT+ 0x0070))#define INCA_IP_WDT_MANID_MANUF (value) (((( 1 << 11) - 1) & (value)) << 5) /***Chip Identification Register***/ #define INCA_IP_WDT_CHIPID ((volatile u32*)(INCA_IP_WDT+ 0x0074))#define INCA_IP_WDT_CHIPID_VERSION (value) (((( 1 << 4) - 1) & (value)) << 28)#define INCA_IP_WDT_CHIPID_PART_NUMBER (value) (((( 1 << 16) - 1) & (value)) << 12)#define INCA_IP_WDT_CHIPID_MANID (value) (((( 1 << 11) - 1) & (value)) << 1) /***Redesign Tracing Identification Register***/ #define INCA_IP_WDT_RTID ((volatile u32*)(INCA_IP_WDT+ 0x0078))#define INCA_IP_WDT_RTID_LC (1 << 15)#define INCA_IP_WDT_RTID_RIX (value) (((( 1 << 3) - 1) & (value)) << 0) /***Watchdog Timer Control Register 0***/ #define INCA_IP_WDT_WDT_CON0 ((volatile u32*)(INCA_IP_WDT+ 0x0020)) /***Watchdog Timer Control Register 1***/ #define INCA_IP_WDT_WDT_CON1 ((volatile u32*)(INCA_IP_WDT+ 0x0024))#define INCA_IP_WDT_WDT_CON1_WDTDR (1 << 3)#define INCA_IP_WDT_WDT_CON1_WDTIR (1 << 2) /***Watchdog Timer Status Register***/ #define INCA_IP_WDT_WDT_SR ((volatile u32*)(INCA_IP_WDT+ 0x0028))#define INCA_IP_WDT_WDT_SR_WDTTIM (value) (((( 1 << 16) - 1) & (value)) << 16)#define INCA_IP_WDT_WDT_SR_WDTPR (1 << 5)#define INCA_IP_WDT_WDT_SR_WDTTO (1 << 4)#define INCA_IP_WDT_WDT_SR_WDTDS (1 << 3)#define INCA_IP_WDT_WDT_SR_WDTIS (1 << 2)#define INCA_IP_WDT_WDT_SR_WDTOE (1 << 1)#define INCA_IP_WDT_WDT_SR_WDTAE (1 << 0) /***********************************************************************//* Module : CGU register address and bits *//***********************************************************************/ #define INCA_IP_CGU (0xBF107000)/***********************************************************************/ /***CGU PLL1 Control Register***/ #define INCA_IP_CGU_CGU_PLL1CR ((volatile u32*)(INCA_IP_CGU+ 0x0008))#define INCA_IP_CGU_CGU_PLL1CR_SWRST (1 << 31)#define INCA_IP_CGU_CGU_PLL1CR_EN (1 << 30)#define INCA_IP_CGU_CGU_PLL1CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16)#define INCA_IP_CGU_CGU_PLL1CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0) /***CGU PLL0 Control Register***/ #define INCA_IP_CGU_CGU_PLL0CR ((volatile u32*)(INCA_IP_CGU+ 0x0000))#define INCA_IP_CGU_CGU_PLL0CR_SWRST (1 << 31)#define INCA_IP_CGU_CGU_PLL0CR_EN (1 << 30)#define INCA_IP_CGU_CGU_PLL0CR_NDIV (value) (((( 1 << 6) - 1) & (value)) << 16)#define INCA_IP_CGU_CGU_PLL0CR_MDIV (value) (((( 1 << 4) - 1) & (value)) << 0) /***CGU PLL0 Status Register***/ #define INCA_IP_CGU_CGU_PLL0SR ((volatile u32*)(INCA_IP_CGU+ 0x0004))#define INCA_IP_CGU_CGU_PLL0SR_LOCK (1 << 31)#define INCA_IP_CGU_CGU_PLL0SR_RCF (1 << 29)#define INCA_IP_CGU_CGU_PLL0SR_PLLBYP (1 << 15) /***CGU PLL1 Status Register***/ #define INCA_IP_CGU_CGU_PLL1SR ((volatile u32*)(INCA_IP_CGU+ 0x000C))#define INCA_IP_CGU_CGU_PLL1SR_LOCK (1 << 31)#define INCA_IP_CGU_CGU_PLL1SR_RCF (1 << 29)#define INCA_IP_CGU_CGU_PLL1SR_PLLBYP (1 << 15) /***CGU Divider Control Register***/ #define INCA_IP_CGU_CGU_DIVCR ((volatile u32*)(INCA_IP_CGU+ 0x0010)) /***CGU Multiplexer Control Register***/ #define INCA_IP_CGU_CGU_MUXCR ((volatile u32*)(INCA_IP_CGU+ 0x0014))#define INCA_IP_CGU_CGU_MUXCR_SWRST (1 << 31)#define INCA_IP_CGU_CGU_MUXCR_MUXII (1 << 1)#define INCA_IP_CGU_CGU_MUXCR_MUXI (1 << 0) /***CGU Fractional Divider Control Register***/ #define INCA_IP_CGU_CGU_FDCR ((volatile u32*)(INCA_IP_CGU+ 0x0018))#define INCA_IP_CGU_CGU_FDCR_FDEN (1 << 31)#define INCA_IP_CGU_CGU_FDCR_INTEGER (value) (((( 1 << 12) - 1) & (value)) << 16)#define INCA_IP_CGU_CGU_FDCR_FRACTION (value) (((( 1 << 16) - 1) & (value)) << 0) /***********************************************************************//* Module : PMU register address and bits *//***********************************************************************/ #define INCA_IP_PMU (0xBF102000)/***********************************************************************/ /***PM Global Enable Register***/ #define INCA_IP_PMU_PM_GEN ((volatile u32*)(INCA_IP_PMU+ 0x0000))#define INCA_IP_PMU_PM_GEN_EN16 (1 << 16)#define INCA_IP_PMU_PM_GEN_EN15 (1 << 15)#define INCA_IP_PMU_PM_GEN_EN14 (1 << 14)#define INCA_IP_PMU_PM_GEN_EN13 (1 << 13)#define INCA_IP_PMU_PM_GEN_EN12 (1 << 12)#define INCA_IP_PMU_PM_GEN_EN11 (1 << 11)#define INCA_IP_PMU_PM_GEN_EN10 (1 << 10)#define INCA_IP_PMU_PM_GEN_EN9 (1 << 9)#define INCA_IP_PMU_PM_GEN_EN8 (1 << 8)#define INCA_IP_PMU_PM_GEN_EN7 (1 << 7)#define INCA_IP_PMU_PM_GEN_EN6 (1 << 6)#define INCA_IP_PMU_PM_GEN_EN5 (1 << 5)#define INCA_IP_PMU_PM_GEN_EN4 (1 << 4)#define INCA_IP_PMU_PM_GEN_EN3 (1 << 3)#define INCA_IP_PMU_PM_GEN_EN2 (1 << 2)#define INCA_IP_PMU_PM_GEN_EN0 (1 << 0) /***PM Power Down Enable Register***/ #define INCA_IP_PMU_PM_PDEN ((volatile u32*)(INCA_IP_PMU+ 0x0008))#define INCA_IP_PMU_PM_PDEN_EN16 (1 << 16)#define INCA_IP_PMU_PM_PDEN_EN15 (1 << 15)#define INCA_IP_PMU_PM_PDEN_EN14 (1 << 14)#define INCA_IP_PMU_PM_PDEN_EN13 (1 << 13)#define INCA_IP_PMU_PM_PDEN_EN12 (1 << 12)#define INCA_IP_PMU_PM_PDEN_EN11 (1 << 11)#define INCA_IP_PMU_PM_PDEN_EN10 (1 << 10)#define INCA_IP_PMU_PM_PDEN_EN9 (1 << 9)#define INCA_IP_PMU_PM_PDEN_EN8 (1 << 8)#define INCA_IP_PMU_PM_PDEN_EN7 (1 << 7)#define INCA_IP_PMU_PM_PDEN_EN5 (1 << 5)#define INCA_IP_PMU_PM_PDEN_EN4 (1 << 4)#define INCA_IP_PMU_PM_PDEN_EN3 (1 << 3)#define INCA_IP_PMU_PM_PDEN_EN2 (1 << 2)#define INCA_IP_PMU_PM_PDEN_EN0 (1 << 0) /***PM Wake-Up from Power Down Register***/ #define INCA_IP_PMU_PM_WUP ((volatile u32*)(INCA_IP_PMU+ 0x0010))#define INCA_IP_PMU_PM_WUP_WUP16 (1 << 16)#define INCA_IP_PMU_PM_WUP_WUP15 (1 << 15)#define INCA_IP_PMU_PM_WUP_WUP14 (1 << 14)#define INCA_IP_PMU_PM_WUP_WUP13 (1 << 13)#define INCA_IP_PMU_PM_WUP_WUP12 (1 << 12)#define INCA_IP_PMU_PM_WUP_WUP11 (1 << 11)#define INCA_IP_PMU_PM_WUP_WUP10 (1 << 10)#define INCA_IP_PMU_PM_WUP_WUP9 (1 << 9)#define INCA_IP_PMU_PM_WUP_WUP8 (1 << 8)#define INCA_IP_PMU_PM_WUP_WUP7 (1 << 7)#define INCA_IP_PMU_PM_WUP_WUP5 (1 << 5)#define INCA_IP_PMU_PM_WUP_WUP4 (1 << 4)#define INCA_IP_PMU_PM_WUP_WUP3 (1 << 3)#define INCA_IP_PMU_PM_WUP_WUP2 (1 << 2)#define INCA_IP_PMU_PM_WUP_WUP0 (1 << 0) /***PM Control Register***/ #define INCA_IP_PMU_PM_CR ((volatile u32*)(INCA_IP_PMU+ 0x0014))#define INCA_IP_PMU_PM_CR_AWEN (1 << 31)#define INCA_IP_PMU_PM_CR_SWRST (1 << 30)#define INCA_IP_PMU_PM_CR_SWCR (1 << 2)#define INCA_IP_PMU_PM_CR_CRD (value) (((( 1 << 2) - 1) & (value)) << 0) /***********************************************************************//* Module : BCU register address and bits *//***********************************************************************/ #define INCA_IP_BCU (0xB8000100)/***********************************************************************/ ⌨️ 快捷键说明
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