📄 initarm7_7b.s
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;******************************************************************************
;* NORTi3/ARM CPU Startup routirne *
;* *
;* Copyright (c) 1995-2000, MiSPO Co., Ltd. *
;* All rights reserved. *
;* *
;* Assemble : armasm -g -li -cpu ARM7TM -apcs 3/32bit/noswst/nofp/interwork *
;* -PD "ROM_AT_ADDRESS_ZERO SETL {TRUE}" *
;* -PD "STACK SETA 0x??????" *
;* *
;* 04/Aug/1999 *
;* 29/Dec/1999 僗僞僢僋椞堟偺峔惉傪曄峏 *
;* 06/Apr/2000 妱崬傒僄儞僩儕偱 I_Bit偑僙僢僩偝傟偰偄傞応崌偼妱崬傒傪曐棷 *
;******************************************************************************
; Stack size (IRQ mode)
IRQ_STACK EQU 256 ; (MaxInterruptLevel-1)*(StackFrame)+4=6*36+10=226
; Stack size (SVC mode)
SVC_STACK EQU 128 ;
; Program Status Registers
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1b
Mode_SYS EQU 0x1f
I_Bit EQU 0x80
F_Bit EQU 0x40
T_Bit EQU 0x20
CFG_TSTKSZ EQU 60 ; Offset #4*23 in CFG
EXPORT |SWI_Return_Point| ; Return point From Thumb SWI Handler
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$RW$$Limit| ; End of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
IMPORT |CFG|
IMPORT |ISP|
[ :DEF:THUMB
CODE32
]
AREA |_INIT|, CODE, READONLY
EXPORT __main
__main
ENTRY ; Entry point
IF :DEF: ROM_AT_ADDRESS_ZERO ; Locate ROM address 0
b Reset_Handler
b Undefined_Handler
b SWI_Handler
b Prefetch_Handler
b Abort_Handler
nop ; Reserved vector
b IRQ_Handler
b FIQ_Handler
ELSE ; Not 0
nop ; Reserved vector
nop ; Reserved vector
nop ; Reserved vector
nop ; Reserved vector
nop ; Reserved vector
nop ; Reserved vector
nop ; Reserved vector
nop ; Reserved vector
nop ; Reserved vector
nop ; Reserved vector
nop ; Reserved vector
nop ; Reserved vector
nop ; Reserved vector
nop ; Reserved vector
nop ; Reserved vector
nop ; Reserved vector
mov r0, #Mode_SVC:OR:I_Bit:OR:F_Bit
msr cpsr_c,r0
mov r1,#0x8100000
add r1,r1,#0x70000000
mov r2,#0x01
str r2,[r1,#0x04]
str r2,[r1,#0x08]
mov r2,#0x28
str r2,[r1,#0x00]
;map the 16Kbyte 32bit processor sram to zero
mov r1,#0xb8000000
mov r2,#0x3C
mov r3,#0x8 ; 0x08 for external sram, 0x0c for internal sram
str r2,[r1,#0x10]
str r3,[r1,#0x10]
mov r8, #0
adr r9, Vector_Init_Block
ldmia r9!,{r0-r7}
stmia r8!,{r0-r7}
ldmia r9!,{r0-r7}
stmia r8!,{r0-r7}
ENDIF
;************************************************
; RESET HANDLER (Enter on RESET) *
;************************************************
;
; |______|
; |______| <- Bottom of free area (set at sysini)
; |______| .
; |______| .
; |______| .
; |______| CFG.istksz size
; |______| .
; |______| .
; |______| .
; |______| <- ISP stack (IRQ handler)
; |______| .
; |______| .
; |______| IRQ_STACK size
; |______| .
; |______| .
; |______| <- IRQ stack (IRQ entry)
; |______| .
; |______| .
; |______| .
; |______| CFG.tstksz size
; |______| .
; |______| .
; |______| .
; |______| <- TimerHandler stack
; |______| .
; |______| .
; |______| .
; |______| SVC_STACK size
; |______| .
; |______| .
; |______| .
; |______| <- SVC Stack ( = STACK)
Reset_Handler ; The RESET entry point
mov r0, #Mode_SVC:OR:I_Bit:OR:F_Bit
msr cpsr_c,r0
mov r1,#0x8100000
add r1,r1,#0x70000000
mov r2,#0x01
str r2,[r1,#0x04]
str r2,[r1,#0x08]
mov r2,#0x28
str r2,[r1,#0x00]
; --- Initialise memory required by C code
ldr r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
ldr r1, =|Image$$RW$$Base| ; and RAM copy
; ldr r2, =|Image$$RW$$Limit|
ldr r3, =|Image$$ZI$$Base| ; Zero init base => top of initialised data
cmp r0, r1 ; Check that they are different
beq %1
0 cmp r1, r3 ; Copy init data
ldrcc r2, [r0], #4
strcc r2, [r1], #4
bcc %0
1 ldr r1, =|Image$$ZI$$Limit| ; Top of zero init segment
mov r2, #0
2 cmp r3, r1 ; Zero init
strcc r2, [r3], #4
bcc %2
; --- Initialise stack pointer registers
; Enter FIQ mode and set up the FIQ stack pointer
mov R0, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
msr cpsr_c, r0
ldr r13, =STACK ;hcf FIQ_Stack
; Enter ABORT mode and set up the ABORT stack pointer
mov r0, #Mode_ABT:OR:I_Bit:OR:F_Bit ; No interrupts
msr cpsr_c, r0
ldr r13, =STACK
; Enter UNDEFINED mode and set up the UNDEFINED stack pointer
mov r0, #Mode_UND:OR:I_Bit:OR:F_Bit ; No interrupts
msr cpsr_c, r0
ldr r13, =STACK
; Set up the SVC stack pointer last and return to SVC mode
mov r0, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
msr cpsr_c, r0
ldr r13, =STACK
mov r3, #SVC_STACK
sub r2, r13, r3 ; TimerHandler Stack
ldr r3, =CFG
ldr r3, [r3, #CFG_TSTKSZ]
sub r3, r2, r3 ; IRQ Stack
;以下代码用于清除堆栈内的数值。
;当数据段与堆栈不在一起时，会出错。
;***************************************
; mov r4, #0
; mov r5, r2
;4 cmp r5, r1
; strcs r4, [r5], #-4
; bcs %4
;***************************************
; Enter IRQ mode and set up the IRQ stack pointer
mov r0, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
msr cpsr_c, r0
mov r13, r3
mov r4, #IRQ_STACK
sub r3, r3, r4
ldr r4, =ISP
str r3, [r4]
; Now enter USER mode (Idle task)
mov r0, #Mode_USR:OR:I_Bit:OR:F_Bit ; Enter USR mode with
msr cpsr_c, r0 ; disable interrupt
mov r13, r2
; --- Now we enter the C code
IMPORT main
[ :DEF:THUMB
orr r0, pc, #1
bx r0
CODE16 ; Next instruction will be Thumb
]
bl main ; Set ready ... GO!!
; In a real application we wouldn't normally expect to return
END_LOOP
b END_LOOP
[ :DEF:THUMB
CODE32 ; Privilige mode must in ARM mode
]
;******************************************************************************
; *
; Exception handlers *
; *
;******************************************************************************
;************************************************
; SWI Handler (Enter on SWI call) *
;************************************************
SWI_Handler
stmfd sp!,{lr}
mrs lr, spsr
stmfd sp!,{lr}
tst lr, #T_Bit ; Test if bit 5 of SPSR is set
ldr lr, [sp, #4 ] ; Load link register
ldrneh lr, [lr, #-2] ; T_bit set so load halfword(Thumb)
bicne lr, lr, #0xff00 ; and clear top 8 bits of halfword
ldreq lr, [lr, #-4] ; T_bit clear so load word (ARM)
biceq lr, lr, #0xff000000 ; and clear top 8 bits of word
; teq lr, #0x100 ; Kernel call use 0x100
teq lr, #0x00 ; Kernel call use 0x00
bne Not_Kernel
mov pc, a1 ; Jump to Kernel
Not_Kernel
; when not kernel call
;
stmfd sp!,{a1-a4,v1-v8,ip} ; Store Registers
; blanch anywhere you want
; Be suer !! Never break any registers !!
ldmfd sp!, {a1-a4,v1-v8,ip}; Restore Registers
SWI_Return_Point
ldmfd sp!,{lr} ; return from Kernel
msr spsr_c,lr ; but dispatcher will never return
ldmfd sp!,{pc}^
IMPORT |_end_int|
IMPORT |get_irq_func|
;************************************************
; IRQ Handler (Enter on IRQ) *
;************************************************
IRQ_Handler
subs lr, lr, #4 ; return address
stmfd sp!, {lr}
mrs lr, spsr
tst lr, #I_Bit
ldmnefd sp!, {pc}^
stmfd sp!, {a1-a4,ip,lr} ; keep registers
ldr a1, =get_irq_func ; get address of IRQ function
bl IRQ_Handler_call
IRQ_Handler_call
bx a1
;************************************************
; FIQ Handler (Enter on FIQ) *
;************************************************
FIQ_Handler
b FIQ_Handler
; subs pc, lr, #4
;************************************************
; Undefined Handler(Undefined indtruction)*
;************************************************
Undefined_Handler
b Undefined_Handler
; b Reset_Handler
; subs pc, lr, #4
;***************************************************
; Prefetch Handler(instruction address error)*
;***************************************************
Prefetch_Handler
b Prefetch_Handler
; subs pc, lr, #4
;************************************************
; Abotr Handler (Data error) *
;************************************************
Abort_Handler
b Abort_Handler
; subs pc, lr, #8
b Reset_Handler
Vector_Init_Block
ldr pc, Reset_Addr
ldr pc, Undefined_Addr
ldr pc, SWI_Addr
ldr pc, Prefetch_Addr
ldr pc, Abort_Addr
nop ; Reserved vector
ldr pc, IRQ_Addr
ldr pc, FIQ_Addr
Reset_Addr DCD Reset_Handler
Undefined_Addr DCD Undefined_Handler
SWI_Addr DCD SWI_Handler
Prefetch_Addr DCD Prefetch_Handler
Abort_Addr DCD Abort_Handler
DCD 0 ; Reserved vector
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
END
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