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ldr a2, =DELAY
mov a1, #1
strb a1, [a2] ; DELAY = 1;
; When disable interrupt or in interrupt handler
; resume interrupt mask and return
mov a1, #0 ; ercd = E_OK;
ldr ip, =IMASK
ldrh ip, [ip] ; ip = IMASK; (use in dispatch_8)
ands a2, ip, #0x80 ; if(IMASK & 0x0080)
bne dispatch_8 ; return E_OK
ldr a2, =INEST
ldrb a2, [a2]
teq a2, #0 ; if(INSET != 0)
bne dispatch_8 ; return E_OK
ldr a2, =DDISP
ldrb a2, [a2]
teq a2, #0 ; if(DDISP != 0)
bne dispatch_8 ; return E_OK
; Enable interrupt
dispatch_1
mrs a2, cpsr
bic lr, a2, #0x80
msr cpsr_c, lr
msr cpsr_c, a2
ldr a2, =IMASK
strh ip, [a2]
mov ip, a1
; When intrrupt request occured for dispatch to system task
ldr a2, =SDISP ; SDISP = 0 ?
ldrb a2, [a2]
teq a2, #0
ldrne lr, =RDQ
ldrneb a1, [lr]
bne dispatch_4
; When delay dispatch cleared return
ldr a2, =DELAY ; DELAY == 0 ?
ldrb lr, [a2]
teq lr, #0
moveq a1, ip
beq dispatch_8
; Search for next task
dispatch_2
mov lr, #0
strb lr, [a2] ; DELAY = 0
ldr lr, =RDQ
ldrb a1, [lr]
dispatch_3 ; for(rdq = &RDQ[1];;){
ldrb a2, [lr, #1]! ; tid = *rdq++;
teq a2, #0 ; if(tid != 0) break;
beq dispatch_3 ; }
dispatch_4
ldr lr, =RDQ
strb a2, [lr] ; RDQ[0] = tid
teq a1, a2 ; if(RDQ[0] = tid)
mov lr, #TCB_SZ
mul a2, a1, lr
ldr lr, =TCB
ldr lr, [lr]
add a2, a2, lr ; mytcb = &TCB[RDQ[0]]
ldreqb a1, [a2, #TCB_PRI]
ldreq a2, =NOWPRI
streqb a1, [a2]
mov a1, ip ; a1 = ercd
beq dispatch_8
; Keep context
sub lr, sp, #4*12
str lr, [a2, #TCB_SP]
stmfd sp!, {a1-a4,v1-v8} ; a1-a4,v1-v8
; Resume context
ldr v1, =RDQ
ldrb v1, [v1] ; v1 = tid
mov v2, #TCB_SZ
mul v3, v1, v2
ldr v2, =TCB
ldr v4, [v2]
add v2, v3, v4
ldr ip, [v2, #TCB_SP] ; ip = tcb->sp
ldrb v3, [v2, #TCB_PRI] ; v3 = tcb->pri
ldr v4, =NOWPRI
strb v3, [v4] ; NOWPRI = tcb->pri
mrs a1, cpsr
bic a1, a1, #0x0c
msr cpsr_c, a1
add v1, ip, #16*4
stmfd sp!, {v1}
ldmfd sp, {sp}^
nop
add sp, sp, #4
ldmfd ip, {a1-a4,v1-v8,lr}^
nop
add ip, ip, #13*4
ldmfd ip!, {lr}
msr spsr_cf,lr
mov lr, ip
ldmfd lr!, {ip}
ldmfd lr!, {pc}^
; Resume interrupt mask and return
dispatch_8
ldmfd sp!, {lr}
ldmfd sp!, {a2, a3, a4}
ldr ip, =IMASK
ldrh ip, [ip]
orr a2, a2, ip
mrs ip, cpsr
bic ip, ip, #0x0c
msr cpsr_c, ip
stmfd sp!, {a2, a4}
ldr lr, =SWI_Return_Point
bx lr
; Without check INEST/IMASK/DDISP
_dispatch1
ldmfd sp!, {a2, a3}
mrs ip, cpsr
orr ip, ip, #0x1f
msr cpsr_c, ip
bic a1, a2, #0xc0
stmfd sp!, {a1, a2, a3}
stmfd sp!, {lr}
ldr a1, =CTXPTN
ldr a3, [a1]
ldr a1, =CTXPTR
ldr a4, [a1]
mov a1, #1
ldr a2, =DELAY
strb a1, [a2] ; DELAY = 1;
mov a1, #0
ldr ip, =IMASK
ldrh ip, [ip]
b dispatch_1
; Dispatch whith no check (syssta, chg_ims 梡乯
_dispatch2
ldmfd sp!, {a2, a3}
mrs ip, cpsr
orr ip, ip, #0x1f
msr cpsr_c, ip
bic a1, a2, #0xc0
stmfd sp!, {a1, a2, a3}
stmfd sp!, {lr}
ldr a2, =DELAY
mov ip, #0
b dispatch_2
; no save context and dispatch
_dispatch3
add sp, sp, #4*2
ldr lr, =RDQ
ldrb a1, [lr]
dispatch_6 ; for(rdq = &RDQ[1];;){
ldrb a2, [lr, #1]! ; tid = *rdq++;
teq a2, #0 ; if(tid != 0) break;
beq dispatch_6 ; }
ldr v1, =RDQ
strb a2, [v1] ; RDQ[0] = tid
ldrb v1, [v1] ; v1 = tid
mov v2, #TCB_SZ
mul v3, v1, v2
ldr v2, =TCB
ldr v4, [v2]
add v2, v3, v4
ldr ip, [v2, #TCB_SP] ; ip = tcb->sp
ldrb v3, [v2, #TCB_PRI] ; v3 = tcb->pri
ldr v4, =NOWPRI
strb v3, [v4] ; NOWPRI = tcb->pri
add v1, ip, #16*4
stmfd sp!, {v1}
ldmfd sp, {sp}^
nop
add sp, sp, #4
ldmfd ip, {a1-a4,v1-v8,lr}^
nop
add ip, ip, #13*4
ldmfd ip!, {lr}
msr spsr_cf,lr
mov lr, ip
ldmfd lr!, {ip}
ldmfd lr!, {pc}^
dispatch_call
bx a1
;************************************************
;* Interrupt mask *
;************************************************
EXPORT _dis_ims
ALIGN 4
_dis_ims ; void dis_ims(void)
stmfd sp!, {v1,v2}
ldr v1, [sp, #2*4]
ldr v2, =KNL_SR
ldrh lr, [v2]
bic v2, v1, #0xc0
orr v2, v2, lr
str v2, [sp, #2*4]
ldr v2, =IMASK
and v1, v1, #0xc0
strh v1, [v2]
ldmfd sp!, {v1,v2}
ldr lr, =SWI_Return_Point
bx lr
;************************************************
;* Resume interrupt mask *
;************************************************
EXPORT _ret_ims
ALIGN 4
_ret_ims ; ER ret_ims(void)
ldr a1, [sp, #0*4]
bic a1, a1, #0xc0
ldr lr, =IMASK
ldrh lr, [lr]
orr a1, a1, lr
str a1, [sp, #0*4]
mov a1, #0
ldr lr, =SWI_Return_Point
bx lr
EXPORT _ret_ims2
ALIGN 4
_ret_ims2 ; void ret_ims2(void)
ldr a1, [sp, #0*4]
bic a1, a1, #0xc0
ldr lr, =IMASK
ldrh lr, [lr]
orr a1, a1, lr
str a1, [sp, #0*4]
ldr lr, =SWI_Return_Point
bx lr
;************************************************
;* Open and close interrupt mask *
;************************************************
EXPORT _ope_ims
ALIGN 4
_ope_ims
ldmfd sp!, {a3,a4}
mrs a1, cpsr
orr lr, a1, #0x0f
bic ip, lr, #0xc0
ldr lr, =IMASK
ldrh a2, [lr]
orr ip, a2, ip
msr cpsr_c, ip
msr cpsr_c, a1
ldr ip, =IMASK
strh a2, [ip]
stmfd sp!, {a3,a4}
ldr lr, =SWI_Return_Point
bx lr
;******************************************************************************
;* *
;* NORTi Unique functions *
;* *
;******************************************************************************
;********************************************************
;* Interrupt mask clear (status register) *
;********************************************************
EXPORT _vdis_psw
ALIGN 4
_vdis_psw ; UINT vdis_psw(void)
ldr lr, [sp, #0]
and a1, lr, #0xc0
orr lr, lr, #0x80
str lr, [sp, #0]
ldr lr, =SWI_Return_Point
bx lr
;************************************************
;* Interrupt mask set (status reigster) *
;************************************************
EXPORT _vset_psw
ALIGN 4
_vset_psw ; void vset_psw(UINT psw)
ldr a1, [sp, #0]
bic a1, a1, #0xc0
orr a1, a1, a2
str a1, [sp, #0]
ldr lr, =SWI_Return_Point
bx lr
;******************************************************************************
;* *
;* addresses/data definition *
;* *
;******************************************************************************
;CODE32
AREA |C$$data|, DATA
;* External reference
STARTOF_STACK DCD |Image$$RW$$Limit|
TCB DCD _TCB - TCB_SZ
END
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