📄 n3darm.s
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;******************************************************************************
;* NORTi3/ARM CPU Interface Module *
;* *
;* Copyright (c) 1995-2001, MiSPO Co., Ltd. *
;* All rights reserved. *
;* *
;* Assemble : *
;* armasm -li -cpu ARM7TDMI -apcs 3/noswst/nofp/interwork n3darm.s *
;* tasm -32 -li -cpu ARM7TDMI -apcs 3/noswst/nofp/interwork n3darm.s *
;* *
;* 04/Aug/1999 *
;* 06/Dec/1999 僔僗僥儉僐乕儖撪偺妱崬傒暅婣偱僨傿僗僷僢僠偡傞傛偆偵廋惓 *
;* 09/Mar/2000 IRQ僗僞僢僋憖嶌偺岆傝傪廋惓 *
;* 06/Apr/2000 僶乕僕儑儞掕媊僥乕僽儖傪4僶僀僩僶僂儞僟儕偵廋惓 *
;* 04/Jul/2000 dispatch 娭悢撪偱偼lr儗僕僗僞傪攋夡偟側偄傛偆偵廋惓 *
;******************************************************************************
TCB_SZ EQU 28
TCB_SP EQU 0
TCB_PRI EQU 4
;* External Symbols
IMPORT KNL_SR
IMPORT intini
IMPORT c_sysini
IMPORT wup_tsk
IMPORT clr_in_service
IMPORT RDQ ; eady queue
IMPORT IMASK ; interrupt mask
IMPORT INEST ; interrupt nest counter
IMPORT DELAY ; request delay dispatch
IMPORT ISP ; Initial value of interrupt stack
IMPORT NOWPRI ; Priority of current task
IMPORT DDISP ; Disable dispatch
IMPORT SDISP ; Request dispatch for Systerm task
IMPORT CTXPTN
IMPORT CTXPTR
IMPORT _TCB ; Arrey for TCB
IMPORT |Image$$RW$$Limit|
IMPORT SWI_Return_Point
AREA |C$$code|, CODE, READONLY
;************************************************
;* 僶乕僕儑儞偺掕媊 *
;************************************************
ALIGN 4
DCB "NORTi(c)MiSPO",0
ALIGN 4
EXPORT _NORTI_VER
_NORTI_VER ; T_VER _NORTI_VER;
DCW 0x0108 ; Maker No乮MiSPO乯
DCW 0x0000 ; 乮NORTi/ARM乯
DCW 0x5300 ; 巇條彂僶乕僕儑儞乮兪ITRON巇條彂Ver3.00乯
DCW 0x0309 ; 惢昳僶乕僕儑儞乮Ver3.09乯
DCW 0x0000 ; 惢昳娗棟忣曬
DCW 0x0000 ; 惢昳娗棟忣曬
DCW 0x0000 ; 惢昳娗棟忣曬
DCW 0x0000 ; 惢昳娗棟忣曬
DCW 0x0000 ; 俠俹倀忣曬乮ARM乯
DCW 0x8000 ; 僶儕僄乕僔儑儞婰弎乮儗儀儖S乯
;******************************************************************************
;* *
;* System call functions *
;* *
;******************************************************************************
;************************************************
;* Initialize system *
;************************************************
EXPORT sysini
ALIGN 4
sysini ; void sysini(void)
mov a2, sp ; nowsp
stmfd sp!, {lr} ; keep return address
ldr a1, =STARTOF_STACK
ldr a1, [a1] ; stktop
ldr a3, =c_sysini
bl sysini_call ; c_sysini(stktop, nowsp);
ldr a3, =intini
bl sysini_call ; ER intini(void)
ldmfd sp!, {lr}
bx lr ; return to main
sysini_call
bx a3
;************************************************
;* Start Interrupt Handler *
;************************************************
; IRQ Stack only interrupt nest
; |______| |______|
; |______| + 0|_U_lr_|
; |______| + 4|______| <- Saved by IRQ_Func (Never USE)
; + 0|__a1__| <- Saved by + 8|__a1__|
; + 4|__a2__| <- IRQ Handler +12|__a2__|
; + 8|__a3__| <- . +16|__a3__|
; +12|__a4__| <- . +20|__a4__|
; +16|__ip__| <- . +24|__ip__|
; +20|_spsr_| <- . +28|_spsr_|
; +24|__lr__| <- . +32|__lr__|
;
EXPORT ent_int
ALIGN 4
ent_int ; void ent_int(void)
IF :DEF: __ADS
IF {ARMASM_VERSION} < 110000
stmfd sp, {lr}^ ; lr_USR
sub sp, sp, #4*1
ELSE
stmed sp, {lr}^ ; lr_USR
ENDIF
ELSE
stmfd sp, {lr}^ ; lr_USR
sub sp, sp, #4*1
ENDIF
stmfd sp!, {lr}
ldmfd sp, {lr}^
nop
add sp, sp, #4*1
ldr a1, =INEST ; INEST --
ldrb a2, [a1]
teq a2, #0
sub a2, a2, #1
strb a2, [a1]
bne ent_int_3
ldr a3, =RDQ
ldrb a3, [a3]
mov a4, #TCB_SZ
mul a1, a3, a4
ldr a4, =TCB
ldr a3, [a4]
add a1, a3, a1
stmfd sp, {sp}^
ldr ip, [sp, #-4] ; ip = USR_sp
sub a2, ip, #16*4
str a2, [a1, #TCB_SP]
add a1, sp, #6*4
ldmfd a1, {a2,a3,a4}
mov a1, a3
stmfd ip!, {a1,a2,a4} ; cpsr, ip, USR_pc
ldr lr, [sp] ; USR_lr
add sp, sp, #2*4
ldmfd sp!, {a1-a4}
stmfd ip!, {a1-a4,v1-v8,lr}
ldr a1, =ISP
ldr a1, [a1]
stmfd sp!, {a1}
ldmfd sp, {sp}^
nop
add sp, sp, #4*1
ent_int_3
mrs a1, cpsr
bic a1, a1, #0x8f ; Prepare mode
; user mode enable interrupt
msr cpsr_c, a1 ; goto user mode
ent_int_call
bx lr
;************************************************
;* Return form Interrupt handler *
;************************************************
; ret_wup describe in n3rarm.h
; #define ret_wup { wup_tsk(); ret_int(); }
; Because _ret_int is SWI handler
EXPORT _ret_int
ALIGN 4
_ret_int ; void ret_int(void)
add sp, sp, #2*4 ; saved by SWI_Handler
mrs ip, cpsr
bic ip, ip, #0x01 ; To IRQ mode
msr cpsr_c, ip
ldr a1, =clr_in_service
bl end_int_call
ldr a1, =INEST ; INEST++
ldrb a2, [a1]
add a2, a2, #1
strb a2, [a1]
;************************************************
;* Return form interrupt and dispatch *
;************************************************
; IRQ Stack T_CTX Structuer
; |______| |______|
; |______| + 0|__a1__|<- TCB[RDQ[tskid]].sp
; |______| + 4|__a2__|
; |______| + 8|__a3__|
; |______| +12|__a4__|
; |______| ------> +16|__v1__|
; |______| +20|__v2__|
; |______| +24|__v3__|
; + 0|_U_lr_| +28|__v4__|
; + 4|______| +32|__v5__|
; + 8|__a1__| +36|__v6__|
; +12|__a2__| +40|__v7__|
; +16|__a3__| +44|__v8__|
; +20|__a4__| +48|__lr__|
; +24|__ip__| +52|_cpsr_|
; +28|_spsr_| +56|__ip__|
; +30|__pc__| +60|__pc__|
_end_int
ldr a1, =INEST ; if(INEST != 0)
ldrb a1, [a1]
teq a1, #0
bne end_int_8
ldr a2, [sp,#4*1] ; if((妱傝崬傒帪偺 SPSR & 0xc0) == 0)
add sp, sp, #4*3
ands a2, a2, #0xc0
bne end_int_4 ; return
ldr a1, =DDISP
ldrb a1, [a1]
teq a1, #0 ; if (DDISP)
bne end_int_4 ; return
ldr a1, =SDISP
ldrb a2, [a1] ; tid = SDISP;
ldr a1, =RDQ
teq a2, #0
bne end_int_3 ; if (SDISP == 0){
ldr a2, =DELAY ; if (DELAY != 0)
ldrb a3, [a2]
teq a3, #0
beq end_int_4 ; return
mov a3, #0
strb a3, [a2] ; DELAY = 0;
mov a4, a1
end_int_2 ; for (rdq = &RDQ[1];;) {
ldrb a2, [a4, #1]! ; tid = *rdq++;
teq a2, #0 ; if(tid != 0) break;
beq end_int_2 ; }
end_int_3 ; }
; a1 = &RDQ[0] , a2 = next task
strb a2, [a1] ; RDQ[0] = tid
; Resume context
end_int_4
ldr a1, =RDQ
ldrb a1, [a1] ; a1 = tid
mov a2, #TCB_SZ
mul a3, a1, a2
ldr a2, =TCB
ldr a4, [a2]
add a2, a3, a4
ldr ip, [a2, #TCB_SP] ; ip = tcb->sp
ldrb a3, [a2, #TCB_PRI] ; a3 = tcb->pri
ldr a4, =NOWPRI
strb a3, [a4] ; NOWPRI = tcb->pri
add a1, ip, #16*4
stmfd sp!, {a1}
ldmfd sp, {sp}^
nop
add sp, sp, #4
ldmfd ip, {a1-a4,v1-v8,lr}^
nop
add ip, ip, #13*4
ldmfd ip!, {lr}
msr spsr_cf,lr
mov lr, ip
ldmfd lr!, {ip}
ldmfd lr!, {pc}^
end_int_8
ldmfd sp, {lr}^ ; lr_USR
nop
add sp, sp, #4*2 ; USR registers and saved by int func
ldr a1, [sp, #5*4]
msr spsr_cf,a1
ldmfd sp!,{a1-a4,ip}
add sp, sp, #1*4
ldmfd sp!,{pc}^
end_int_call
bx a1
;******************************************************************************
;* *
;* Kernel internal functions *
;* *
;******************************************************************************
;************************************************
;* Dispatch *
;************************************************
; T_CTX 峔憿懱
; |______| + 0|__a1__| (ercd) <- TCB[RDQ[0]].sp
; |______| + 4|__a2__|
; |______| + 8|__a3__| (CTXPTN)
; |______| +12|__a4__| (CTXPTR)
; |______| +16|__v1__|
; |______| +20|__v2__|
; |______| +24|__v3__|
; |______| -----> +28|__v4__|
; |______| +32|__v5__|
; |______| +36|__v6__|
; |______| +40|__v7__|
; |______| +44|__v8__|
; |______| +48|__lr__|
; |______| +52|_cpsr_|
; |______| +56|__ip__|
; |______| +60|__pc__|
EXPORT _dispatch
EXPORT _dispatch1
EXPORT _dispatch2
EXPORT _dispatch3
ALIGN 4
_dispatch ; ER dispatch(void)
ldmfd sp!, {a2, a3}
mrs ip, cpsr
orr ip, ip, #0x1f
msr cpsr_c, ip
bic a1, a2, #0xc0
stmfd sp!, {a1, a2, a3}
stmfd sp!, {lr}
; Request for delay dispatch
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