📄 okimpla2.h
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#define DC_BASE 0x78180000 /* Base address */
#define DBWC (DC_BASE+0x00) /* DRAM bus width control register */
#define DRMC (DC_BASE+0x04) /* DRAM control register */
#define DRPC (DC_BASE+0x08) /* DRAM parameter control register */
#define SDMD (DC_BASE+0x0C) /* SDRAM mode register */
#define DCMD (DC_BASE+0x10) /* DRAM command register */
#define RFSH (DC_BASE+0x14) /* DRAM refresh cycle control register */
#define PDWC (DC_BASE+0x18) /* SDRAM power down control register */
/* Bit field of DBWC register */
#define DBWC_UM 0x00 /* Un-mounted */
#define DBWC_8bit 0x01 /* 8bit width */
#define DBWC_16bit 0x02 /* 16bit width */
#define DBWC_32bit 0x03 /* 32bit width */
/* Bit field of DRMC register */
#define DRMC_8bit 0x00 /* DRAM column length : 8bit */
#define DRMC_9bit 0x01 /* DRAM column length : 9bit */
#define DRMC_10bit 0x02 /* DRAM column length : 10bit */
#define DRMC_SDRAM 0x00 /* DRAM architecture : SDRAM */
#define DRMC_EDO 0x04 /* DRAM architecture : EDO-DRAM */
#define DRMC_2CLK 0x00 /* SDRAM pre-charge latency : 2clock */
#define DRMC_CAS 0x08 /* SDRAM pre-charge latency : Same as CAS latency */
#define DRMC_PD_DIS 0x00 /* Automatic shift to SDRAM power down mode : disable */
#define DRMC_PD_EN 0x10 /* Automatic shift to SDRAM power down mode : enable */
#define DRMC_RF_STOP 0x00 /* CBR refresh : stop */
#define DRMC_RF_EXE 0x20 /* CBR refresh : execution */
/* Bit field of SDMD register */
#define SDMD_CL2 0x00 /* SDRAM CAS latency : 2 */
#define SDMD_CL3 0x01 /* SDRAM CAS latency : 3 */
#define SDMD_INV 0x00 /* Setting operation : invalid */
#define SDMD_VALID 0x80 /* Setting operation : valid */
/* Bit field of DCMD register */
#define DCMD_S_PALL 0x04 /* SDRAM All bank pre-charge command */
#define DCMD_S_REF 0x05 /* SDRAM CBR refresh command */
#define DCMD_S_SELF 0x06 /* SDRAM Self refresh start command */
#define DCMD_S_SREX 0x07 /* SDRAM Self refresh stop command */
#define DCMD_EDO_PC 0x04 /* EDO-DRAM pre-charge cycle */
#define DCMD_EDO_REF 0x05 /* EDO-DRAM CBR refresh cycle */
#define DCMD_EDO_SELF 0x06 /* EDO-DRAM self refresh start cycle */
#define DCMD_EDO_SREX 0x07 /* EDO-DRAM self refresh stop cycle */
/* Bit field of RFSH register */
#define RFSH_DOUBLE 0x00 /* Refresh frequency = refreqa * 2 */
#define RFSH_SINGLE 0x01 /* Refresh frequency = refreqa */
/* Bit field of PDWC register */
#define PDWC_1 0x00 /* When 1 or more cycles of idol State continue,
it shifts to power down mode. */
#define PDWC_2 0x01 /* : */
#define PDWC_3 0x02 /* : */
#define PDWC_4 0x03 /* : */
#define PDWC_5 0x04 /* : */
#define PDWC_6 0x05 /* : */
#define PDWC_7 0x06 /* : */
#define PDWC_8 0x07 /* : */
#define PDWC_9 0x08 /* : */
#define PDWC_10 0x09 /* : */
#define PDWC_11 0x0A /* : */
#define PDWC_12 0x0B /* : */
#define PDWC_13 0x0C /* : */
#define PDWC_14 0x0D /* : */
#define PDWC_15 0x0E /* : */
#define PDWC_16 0x0F /* When 16 or more cycles of idol State continue,
it shifts to power down mode. */
/*------------------------------ Prototyping Board --------------------------------*/
/*****************************************************/
/* UART control register */
/*****************************************************/
#define UC_BASE 0xB7B00000 /* Base address */
#define RBR (BYTE *)(UC_BASE+0x00) /* Receiver Buffer Register */
#define THR (BYTE *)(UC_BASE+0x00) /* Transmitter Buffer Register */
#define IER (BYTE *)(UC_BASE+0x04) /* Interrupt Enable Register */
#define IIR (BYTE *)(UC_BASE+0x08) /* Interrupt Identification */
#define FCR (BYTE *)(UC_BASE+0x08) /* FIFO Control Register */
#define LCR (BYTE *)(UC_BASE+0x0C) /* Line Control Register */
#define MCR (BYTE *)(UC_BASE+0x10) /* Modem Control Register */
#define LSR (BYTE *)(UC_BASE+0x14) /* Line Status Register */
#define MSR (BYTE *) (UC_BASE+0x18) /* Modem Status Register */
#define SCR (BYTE *)(UC_BASE+0x1C) /* Scratchpad Register */
#define DLL (BYTE *)(UC_BASE+0x00) /* Divisor Latch(LSB) */
#define DLM (BYTE *) (UC_BASE+0x04) /* Divisor Latch(MSB) */
#define DLH (BYTE *)(UC_BASE+0x08) /* Divisor Latch(HSB) */
/*** add by dsw ***/
/*****************************************************/
/* UART1 control register */
/*****************************************************/
#define UC_BASE1 0xB7B80000 /* Base address */
#define UART1_RBR (BYTE *)(UC_BASE1+0x00) /* Receiver Buffer Register */
#define UART1_THR (BYTE *)(UC_BASE1+0x00) /* Transmitter Buffer Register */
#define UART1_IER (BYTE *)(UC_BASE1+0x04) /* Interrupt Enable Register */
#define UART1_IIR (BYTE *)(UC_BASE1+0x08) /* Interrupt Identification */
#define UART1_FCR (BYTE *)(UC_BASE1+0x08) /* FIFO Control Register */
#define UART1_LCR (BYTE *)(UC_BASE1+0x0C) /* Line Control Register */
#define UART1_MCR (BYTE *)(UC_BASE1+0x10) /* Modem Control Register */
#define UART1_LSR (BYTE *)(UC_BASE1+0x14) /* Line Status Register */
#define UART1_MSR (BYTE *) (UC_BASE1+0x18) /* Modem Status Register */
#define UART1_SCR (BYTE *)(UC_BASE1+0x1C) /* Scratchpad Register */
#define UART1_DLL (BYTE *)(UC_BASE1+0x00) /* Divisor Latch(LSB) */
#define UART1_DLM (BYTE *) (UC_BASE1+0x04) /* Divisor Latch(MSB) */
#define UART1_DLH (BYTE *)(UC_BASE+0x08) /* Divisor Latch(HSB) */
/*** add end ***/
/* Bit field of LCR register */
#define LCR_LEN5 0x0000 /* Data length : 5bit */
#define LCR_LEN6 0x0001 /* Data length : 6bit */
#define LCR_LEN7 0x0002 /* Data length : 7bit */
#define LCR_LEN8 0x0003 /* Data length : 8bit */
#define LCR_STB1 0x0000 /* Stop bit : 1 */
#define LCR_STB2 0x0004 /* Stop bit : 2(data length 6-8) */
#define LCR_STB1_5 0x0004 /* Stop bit : 1.5(data length 5) */
#define LCR_PEN 0x0008 /* Parity enabled */
#define LCR_PDIS 0x0000 /* Parity disabled */
#define LCR_EVN 0x0010 /* Even parity */
#define LCR_ODD 0x0000 /* Odd parity */
#define LCR_SP 0x0020 /* Stick parity */
#define LCR_BRK 0x0040 /* Break delivery */
#define LCR_DLAB 0x0080 /* Devisor latch access bit */
/* Bit field of LSR register */
#define LSR_DR 0x0001 /* Data ready */
#define LSR_OE 0x0002 /* Overrun error */
#define LSR_PE 0x0004 /* Parity error */
#define LSR_FE 0x0008 /* Framing error */
#define LSR_BI 0x0010 /* Break interrupt */
#define LSR_THRE 0x0020 /* Transmitter holding register empty */
#define LSR_TEMT 0x0040 /* Transmitter empty */
#define LSR_ERF 0x0080 /* Receiver FIFO error */
/* Bit field of FCR register */
#define FCR_FE 0x0001 /* FIFO enable */
#define FCR_FD 0x0000 /* FIFO disable */
#define FCR_RFCLR 0x0002 /* Receiver FIFO clear */
#define FCR_TFCLR 0x0004 /* Transmitter FIFO clear */
#define FCR_DMA_S 0x0008 /* DMA Single Transmission Mode */
#define FCR_DMA_D 0x0000 /* DMA Dual Transmission Mode */
#define FCR_RFLV1 0x0000 /* RCVR FIFO interrupt trigger level : 1byte */
#define FCR_RFLV32 0x0040 /* RCVR FIFO interrupt trigger level : 32byte */
#define FCR_RFLV64 0x0080 /* RCVR FIFO interrupt trigger level : 64byte */
#define FCR_RFLV112 0x00C0 /* RCVR FIFO interrupt trigger level : 112byte */
/* Bit field of MCR register */
#define MCR_DTR 0x0001 /* Data terminal ready */
#define MCR_RTS 0x0002 /* Request to send */
#define MCR_OUT0 0x0004 /* Multipurpose Output Signal 0 */
#define MCR_OUT1 0x0008 /* Multipurpose Output Signal 8 */
#define MCR_LOOP 0x0010 /* Loopback */
/* Bit field of MSR register */
#define MSR_DCTS 0x0001 /* Delta clear to send */
#define MSR_DDSR 0x0002 /* Delta data set ready */
#define MSR_TERI 0x0004 /* Trailing edge of ring endicator */
#define MSR_DDCD 0x0008 /* Delta data carrer detect */
#define MSR_CTS 0x0010 /* Clear to send */
#define MSR_DSR 0x0020 /* Data set ready */
#define MSR_RI 0x0040 /* Ring indicator */
#define MSR_DCD 0x0080 /* Data carrer detect */
/* Bit field of IIR register */
#define IIR_IP 0x0001 /* Interrupt generated */
#define IIR_LINE 0x0006 /* Receiver line status interrupt (Priority:1) */
#define IIR_RCV 0x0004 /* Receiver interrupt (Priority:2) */
#define IIR_TO 0x000C /* Time out interrupt (Priority:2) */
#define IIR_TRA 0x0002 /* Transmitter interrupt (Priority:3) */
#define IIR_MOD 0x0000 /* Modem status interrupt (Priority:4) */
#define IIR_FM 0x00C0 /* FIFO mode */
/* Bit field of IER register */
#define IER_ERBF 0x0001 /* Enable received data available interrupt */
#define IER_ETBEF 0x0002 /* Enable transmitter holding register empty interrupt */
#define IER_ELSI 0x0004 /* Enable receiver line status interrupt */
#define IER_EDSI 0x0008 /* Enable modem status interrupt */
/*****************************************************/
/* PIO control register */
/*****************************************************/
#define PC_BASE 0xB7A00000 /* Base address */
/*****************************************************/
/* Interrupt number */
/*****************************************************/
#define INT_SYSTEM_TIMER 0
#define INT_0 0
#define INT_1 1
#define INT_2 2
#define INT_3 3
#define INT_4 4
#define INT_5 5
#define INT_6 6
#define INT_7 7
#define INT_8 8
#define INT_9 9
#define INT_SIO 10
#define INT_10 10
#define INT_11 11
#define INT_12 12
#define INT_13 13
#define INT_14 14
#define INT_15 15
#if 0
/* Internal I/O macro */
#define sfr_in(n) (*((volatile UB *)(n))) /* 僶僀僩擖椡 */
#define sfr_out(n,c) (*((volatile UB *)(n)) = (c)) /* 僶僀僩弌椡 */
#define sfr_inw(n) (*((volatile UH *)(n))) /* 儚乕僪擖椡 */
#define sfr_outw(n,c) (*((volatile UH *)(n)) = (c)) /* 儚乕僪弌椡 */
#define sfr_inl(n) (*((volatile UW *)(n))) /* 儘儞僌儚乕僪擖椡 */
#define sfr_outl(n,c) (*((volatile UW *)(n)) = (c)) /* 儘儞僌儚乕僪弌椡 */
#define sfr_set(n,c) (*((volatile UB *)(n))|= (c)) /* 僶僀僩價僢僩僙僢僩 */
#define sfr_clr(n,c) (*((volatile UB *)(n))&=~(c)) /* 僶僀僩價僢僩僋儕傾 */
#define sfr_setw(n,c) (*((volatile UH *)(n))|= (c)) /* 儚乕僪價僢僩僙僢僩 */
#define sfr_clrw(n,c) (*((volatile UH *)(n))&=~(c)) /* 儚乕僪價僢僩僋儕傾 */
#define sfr_setl(n,c) (*((volatile UW *)(n))|= (c)) /* 儘儞僌儚乕僪價僢僩僙僢僩 */
#define sfr_clrl(n,c) (*((volatile UW *)(n))&=~(c)) /* 儘儞僌儚乕僪價僢僩僋儕傾 */
#endif
/************************/
#define SIOSTA_BUFOVF 0x80 /* SIO BUFFER OVERFLOW 僶僢僼傽僆乕僶乕僼儘乕 */
/************************/
#ifdef __cplusplus
}; /* End of 'extern "C"' */
#endif
#endif /* End of okimpla2.h */
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