📄 okimpla2.h
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/**********************************************************************************/
/* */
/* Copyright (C) 2001 Oki Electric Industry Co., LTD. */
/* */
/* System Name : uPLAT-7B Prototyping Board */
/* Module Name : Common definition include file for uPLAT-7B PB */
/* File Name : okimpla2.h */
/* Revision : 01.00 */
/* Date : 2001/10/23 New creation */
/* 2001/10/31 Modify description method of addresses */
/* (ADDRESS -> BASE + OFFSET) */
/* Move common definitions to another file */
/* Change file name */
/* Delete some external memory control registers */
/* 2001/11/12 Modify for NORTi */
/* */
/**********************************************************************************/
#ifndef OKIMPLA2_H
#define OKIMPLA2_H
#ifdef __cplusplus
extern "C" {
#endif
#define ML7098
/*------------------------------ uPLAT-7B core -----------------------------------*/
#if 1
/*****************************************************/
/* Interrupt control register */
/*****************************************************/
#define ICR_BASE 0x78000000 /* Base address of interrupt control register */
#define IRQ (ICR_BASE+0x00) /* IRQ Register */
#define IRQS (ICR_BASE+0x04) /* IRQ Soft Register */
#define FIQ (ICR_BASE+0x08) /* FIQ Register */
#define FIQRAW (ICR_BASE+0x0C) /* FIQRAW Status Register */
#define FIQEN (ICR_BASE+0x10) /* FIQ Enable Register */
#define IRN (ICR_BASE+0x14) /* IRQ Number Register */
#define CIL (ICR_BASE+0x18) /* Current IRQ Level Register */
#define IRL (ICR_BASE+0x1C) /* IRQ Level Register */
#define ILC0 (ICR_BASE+0x20) /* IRQ Level Control Register 0 */
#define ILC1 (ICR_BASE+0x24) /* IRQ Level Control Register 1 */
#define CILCL (ICR_BASE+0x28) /* Current IRQ Level Clear Register */
#define CILE (ICR_BASE+0x2C) /* Current IRQ Level Encode Register */
#ifdef DEVICE_uPLAT7_B
#define EICR_BASE 0x7BF00000 /* Base address of extention interrupt control register */
#define EIRQ (EICR_BASE+0x10)/* EIRQ Register */
#define EINTCON (EICR_BASE+0x14)/* EINTCON Register */
#define EILC (EICR_BASE+0x18)/* EILC Register */
#define EINTSTS (EICR_BASE+0x1C)/* EINTSTS Register */
#define KINTSTS (EICR_BASE+0x20)/* KINTSTS Register */
#endif
/* Bit field of IRQ register */
#define IRQ_nIR0 0x00000001 /* nIR[0] */
#define IRQ_nIR1 0x00000002 /* nIR[1] */
#define IRQ_nIR2 0x00000004 /* nIR[2] */
#define IRQ_nIR3 0x00000008 /* nIR[3] */
#define IRQ_nIR4 0x00000010 /* nIR[4] */
#define IRQ_nIR5 0x00000020 /* nIR[5] */
#define IRQ_nIR6 0x00000040 /* nIR[6] */
#define IRQ_nIR7 0x00000080 /* nIR[7] */
#define IRQ_nIR8 0x00000100 /* nIR[8] */
#define IRQ_nIR9 0x00000200 /* nIR[9] */
#define IRQ_nIR10 0x00000400 /* nIR[10] */
#define IRQ_nIR11 0x00000800 /* nIR[11] */
#define IRQ_nIR12 0x00001000 /* nIR[12] */
#define IRQ_nIR13 0x00002000 /* nIR[13] */
#define IRQ_nIR14 0x00004000 /* nIR[14] */
#define IRQ_nIR15 0x00008000 /* nIR[15] */
/* Bit field of CIL register */
#define CIL_INT_LV1 0x00000002 /* Interrupt level 1 */
#define CIL_INT_LV2 0x00000004 /* Interrupt level 2 */
#define CIL_INT_LV3 0x00000008 /* Interrupt level 3 */
#define CIL_INT_LV4 0x00000010 /* Interrupt level 4 */
#define CIL_INT_LV5 0x00000020 /* Interrupt level 5 */
#define CIL_INT_LV6 0x00000040 /* Interrupt level 6 */
#define CIL_INT_LV7 0x00000080 /* Interrupt level 7 */
/* Bit field of ILC0 register */
#define ILC0_INT_LV1 0x01010101 /* Interrupt level 1 */
#define ILC0_INT_LV2 0x02020202 /* Interrupt level 2 */
#define ILC0_INT_LV3 0x03030303 /* Interrupt level 3 */
#define ILC0_INT_LV4 0x04040404 /* Interrupt level 4 */
#define ILC0_INT_LV5 0x05050505 /* Interrupt level 5 */
#define ILC0_INT_LV6 0x06060606 /* Interrupt level 6 */
#define ILC0_INT_LV7 0x07070707 /* Interrupt level 7 */
#define ILC0_ILR0 0x00000007 /* nIR[0] */
#define ILC0_ILR1 0x00000070 /* nIR[1],nIR[2],nIR[3] */
#define ILC0_ILR4 0x00070000 /* nIR[4],nIR[5] */
#define ILC0_ILR6 0x07000000 /* nIR[6],nIR[7] */
/* Bit field of ILC1 register */
#define ILC1_INT_LV1 0x01010101 /* Interrupt level 1 */
#define ILC1_INT_LV2 0x02020202 /* Interrupt level 2 */
#define ILC1_INT_LV3 0x03030303 /* Interrupt level 3 */
#define ILC1_INT_LV4 0x04040404 /* Interrupt level 4 */
#define ILC1_INT_LV5 0x05050505 /* Interrupt level 5 */
#define ILC1_INT_LV6 0x06060606 /* Interrupt level 6 */
#define ILC1_INT_LV7 0x07070707 /* Interrupt level 7 */
#define ILC1_ILR8 0x00000007 /* nIR[8] */
#define ILC1_ILR9 0x00000070 /* nIR[9] */
#define ILC1_ILR10 0x00000700 /* nIR[10] */
#define ILC1_ILR11 0x00007000 /* nIR[11] */
#define ILC1_ILR12 0x00070000 /* nIR[12] */
#define ILC1_ILR13 0x00700000 /* nIR[13] */
#define ILC1_ILR14 0x07000000 /* nIR[14] */
#define ILC1_ILR15 0x70000000 /* nIR[15] */
/* Bit field of CILCL register */
#define CILCL_CLEAR 0x01 /* Most significant '1' bit of CIL is cleared */
/*****************************************************/
/* External Memory control register */
/*****************************************************/
#define EMCR_BASE 0x78100000 /* Base address */
#define BWC (EMCR_BASE+0x00) /* Bus Width Control Register */
#define ROMAC (EMCR_BASE+0x04) /* External ROM Access Control Register */
#define RAMAC (EMCR_BASE+0x08) /* External SRAM Access Control Register */
#define IO0AC (EMCR_BASE+0x0C) /* External IO0 Access Control Register */
#define IO1AC (EMCR_BASE+0x10) /* External IO1 Access Control Register */
#ifdef ML7098
#define EMCR2_BASE 0xB7000000 /* Base address */
#define IOBCC (EMCR2_BASE+0x00) /* External IO Bank Exchange Register */
#endif
/*****************************************************/
/* System control register */
/*****************************************************/
#define SCR_BASE 0xB8000000 /* Base address */
#define IDR (SCR_BASE+0x00) /* ID Register */
#ifdef ML7098
#define CKLSTP (SCR_BASE+0x04) /* Clock Stop Register */
#endif
#define CGBCNT0 (SCR_BASE+0x08) /* Clock(CGB) Control Register 0 */
#define CKWT (SCR_BASE+0x0C) /* Clock Wait Register */
#define RMPCON (SCR_BASE+0x10) /* Remap Control Register */
#define PST (SCR_BASE+0x14) /* Peripheral Status Register */
#define CGBCNT1 (SCR_BASE+0x18) /* Clock(CGB) Control Register 1 */
#define CGBCNT2 (SCR_BASE+0x1C) /* Clock(CGB) Control Register 2 */
#ifdef ML7098
#define SCR2_BASE 0x7BE00000 /* Base address */
#define SRESRQ (SCR2_BASE+0x00)/* Software Reset Request Register */
#define RSTST (SCR2_BASE+0x04)/* Reset Status Register */
#define CGBCNT3 (SCR2_BASE+0x08)/* Clock(CGB) Control Register 3 */
#endif
#endif
/* Bit field of CKSTP/CLKSTP register */
#ifdef ML7098
#define CKLSTP_CPUG 0x04 /* CPU group HALT */
#define CKLSTP_TIC 0x02 /* TIC HALT */
#define CKLSTP_SIO 0x01 /* SIO HALT */
#define CKLSTP_STOP 0xF0 /* Clock stop */
#endif
/* Bit field of CGBCNT0 register */
#define CGBCNT0_CLK1 0x00 /* CPUCLK */
#define CGBCNT0_CLK2 0x01 /* CPUCLK/2 */
#define CGBCNT0_CLK4 0x02 /* CPUCLK/4 */
#define CGBCNT0_CLK8 0x03 /* CPUCLK/8 */
/* Bit field of RMPCON register */
#define RMPCON_ENABLE 0x08 /* Remap enabled */
#define RMPCON_DISABLE 0x00 /* Remap disabled */
#define RMPCON_AHB 0x02 /* Device space is AHB Bus*/
#define RMPCON_EXT 0x00 /* Device space is External Bus */
#define RMPCON_DRAM 0x01 /* Memory type is DRAM */
#define RMPCON_SRAM 0x00 /* Memory type is SRAM */
#ifdef ML7098
#define RMPCON_PROCB 0x04 /* Bus Memory is Proccessor Bus Memory */
#define RMPCON_EXTB 0x00 /* Bus Memory is External Bus Memory */
#endif
/*****************************************************/
/* Timer control register */
/*****************************************************/
#define TC_BASE 0xB8001000 /* Base address */
#define TMEN (TC_BASE+0x04) /* Timer Enable Register */
#define TMRLR (TC_BASE+0x08) /* Timer Reload Register */
#define TMOVF (TC_BASE+0x10) /* Overflow Register */
/* Bit field of TMEN register */
#define TMEN_TCEN 0x01 /* Timer enabled */
/* Bit field of TMOVF register */
#define TMOVF_OVF 0x01 /* Overflow generated */
/*****************************************************/
/* SIO control register */
/*****************************************************/
#define SC_BASE 0xB8002000 /* Base address */
#define SIOBUF (SC_BASE+0x00) /* Transmiting/Receiving Buffer Register */
#define SIOSTA (SC_BASE+0x04) /* SIO Status Registr */
#define SIOCON (SC_BASE+0x08) /* SIO Control Register */
#define SIOBCN (SC_BASE+0x0C) /* Baud Rate Control Register */
#define SIOBTC (SC_BASE+0x10) /* Baud Rate Timer Counter */
#define SIOBT (SC_BASE+0x14) /* Baud Rate Timer Register */
#define SIOTCN (SC_BASE+0x18) /* SIO Test Control Register */
/* Bit field of SIOSTA register */
#define SIOSTA_FERR 0x0001 /* Framing error */
#define SIOSTA_OERR 0x0002 /* Overrun error */
#define SIOSTA_PERR 0x0004 /* Parity error */
#define SIOSTA_RVIRQ 0x0010 /* Receive ready */
#define SIOSTA_TRIRQ 0x0020 /* Transmit ready */
/* Bit field of SIOCON register */
#define SIOCON_LN7 0x0001 /* Data length : 7bit */
#define SIOCON_LN8 0x0000 /* Data length : 8bit */
#define SIOCON_PEN 0x0002 /* Parity enabled */
#define SIOCON_PDIS 0x0000 /* Parity disabled */
#define SIOCON_EVN 0x0004 /* Even parity */
#define SIOCON_ODD 0x0000 /* Odd parity */
#define SIOCON_TSTB1 0x0008 /* Stop bit : 1 */
#define SIOCON_TSTB2 0x0000 /* Stop bit : 2 */
/* Bit field of SIOBCN register */
#define SIOBCN_BGRUN 0x0010 /* Count start */
/* Bit field of SIOTCN register */
#define SIOTCN_MFERR 0x0001 /* Generate framin error */
#define SIOTCN_MPERR 0x0002 /* Generate parity error */
#define SIOTCN_LBTST 0x0080 /* Loop back test */
/*---------------------- uPLAT-7B core optional IP --------------------------------*/
/*****************************************************/
/* DRAMC */
/*****************************************************/
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