xscale_test.c

Intel XScale PXA255 引导Linux的Redboot 版bootloader源代码！

//=============================================================================
//
//      xscale_test.c - Cyclone Diagnostics
//
//=============================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 2001 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   Scott Coulter, Jeff Frazier, Eric Breeden
// Contributors:
// Date:        2001-01-25
// Purpose:     
// Description: 
//
//####DESCRIPTIONEND####
//
//===========================================================================*/

/************************************************************************/
/* iq80310_test.c - Main diagnostics for IQ80310 board					*/
/*																		*/
/* Modification History													*/
/* --------------------													*/
/* 11oct00, ejb, Created for IQ80310 StrongARM2							*/
/* 18dec00  jwf                                                         */
/* 02feb01  jwf	added tests: _coy_tight_loop, cache_loop, LoopMemTest,  */
/*              special_mem_test written by snc							*/     
/* 07feb01  jwf added function calls to a variable delay time generator */
/* 09feb01  jwf added function version_info to show version information */
/*              about OS, BOARD, CPLD, 80200 ID, 80312 ID.              */
/************************************************************************/


#include "7_segment_displays.h"
#include "test_menu.h"
#include "iq80310.h"
#include "pci_bios.h"

extern void read_int_status();
extern void _disableDCache();
extern void _enableDCache();
extern void _enableFiqIrq();
extern void _usec_delay();
extern void _msec_delay();
extern void _enable_timer();
extern void _disable_timer();
extern long _read_timer();
extern long _read_cpsr();

/* 02/02/01 jwf */
extern void _coy_tight_loop();

extern long decIn(void);
extern long hexIn(void);
extern void hex32out(unsigned long num);
extern char* sgets(char *s);

extern void flash_test(void) RAM_FUNC_SECT;

extern STATUS pci_isr_connect (int intline, int bus, int device, int (*handler)(int), int arg);
extern STATUS pci_to_xint(int device, int intpin, int *xint);
extern void timer_test (void);

/* 02/07/01 jwf */
extern void time_delay (UINT32 count, volatile int num_tmr_int);

extern int memTest (long startAddr, long endAddr);

/* 02/02/01 jwf */
extern int LoopMemTest (long	startAddr, long	endAddr);

extern void uart_test(void);
extern void pci_ether_test (UINT32 busno, UINT32 devno, UINT32 funcno);
extern void config_ints(void);	/* configure interrupts */
extern void sys_pci_device_initialization (PCI_DATA* pci_data);
extern STATUS sys_find_pci_device (int vendor_id, int device_id, int index, PCI_DEVICE_LOCATION *devloc);
extern int eeprom_write (unsigned long pci_base, int eeprom_addr, unsigned short *p_data, int nwords);
extern ULONG sys_read_config_dword (UINT32 busno,UINT32 devno,UINT32 funcno,UINT32 offset,UINT32 *data);
extern int enable_external_interrupt (int int_id);
extern int disable_external_interrupt (int int_id);
extern int isr_connect(int int_num, void (*handler)(int), int arg);
extern int isr_disconnect(int int_num);
extern void init_external_timer();
extern void uninit_external_timer();
extern int isHost();

void pci_int_test (void);
void hdwr_diag (void);
void rotary_switch (void);
void seven_segment_display (void);
void backplane_detection(void);
void battery_status(void);
/* void timer_test (void); */
void ether_test (void);
void gpio_test (void);

/* 02/02/01 jwf */
void static cache_loop (void);

/* 02/09/01 jwf */
void version_info (void);
void read_coyanosa_id_reg (void);
char board_revision (void);

static void battery_test_menu (void);
static void battery_test_write (void);
static void battery_test_read (void);

/* 01/11/01 jwf */
void select_host_test_system (void);

void internal_timer(void);
static void enet_setup (void);
static void memory_tests (void);
static void repeat_mem_test (void);

/* 02/02/01 jwf */
static void special_mem_test (void);

static void spci_tests (void), ppci_tests (void);
STATUS Device_Seek(
		int verbose,
		unsigned long adapter_vendor,
		unsigned long adapter_device_id,
		unsigned long dev_index,
    	PCI_DEVICE_LOCATION *dev_info
		);

#define VENDOR_INTEL    	0x8086
#define INTEL_NAME		"Intel Corporation Inc."

#define I80303_BRIDGE	0x0309
#define I80303_NAME0	"80303 PCI-PCI Bridge"

#define I80303_ATU		0x5309
#define I80303_NAME1	"80303 Address Translation Unit"

#define I82557			0x1229
#define I82557_NAME		"82557/82558/82559 10/100 LAN Controller"

#define I82559ER		0x1209
#define I82559ER_NAME	"82559ER 10/100 LAN Controller"


/* Test Menu Table */
static MENU_ITEM testMenu[] =
{
	{"Memory Tests",							memory_tests,		  0},
	{"Repeating Memory Tests",					repeat_mem_test,	  0},
	{"16C552 DUART Serial Port Tests", 			uart_test, 			  0},
	{"Rotary Switch S1 Test",					rotary_switch,		  0},
	{"7 Segment LED Tests",						seven_segment_display,0},
	{"Backplane Detection Test",				backplane_detection,  0},
	{"Battery Status Test",						battery_status,       0},
	{"External Timer Test",						timer_test,           0},
	{"Flash Test",								flash_test,			  0},
	{"i82559 Ethernet Configuration",			enet_setup,			  0},
	{"i82559 Ethernet Test",					ether_test,			  0},
	{"i960Rx/303 PCI Interrupt Test",			pci_int_test,		  0},
	{"Internal Timer Test",						internal_timer,		  0},
	{"Secondary PCI Bus Test",					spci_tests,			  0},
	{"Primary PCI Bus Test",					ppci_tests,			  0},
	{"Battery Backup SDRAM Memory Test",		battery_test_menu,	  0},
	{"GPIO Test",								gpio_test,			  0},
/* 02/02/01 jwf */
	{"Repeat-On-Fail Memory Test",				special_mem_test,	  0},
	{"Coyonosa Cache Loop (No return)",			cache_loop,			  0},
/* 02/09/01 jwf */
	{"Show Software and Hardware Revision",		version_info,		  0}
};

#define NUM_MENU_ITEMS	(sizeof (testMenu) / sizeof (testMenu[0]))

#define MENU_TITLE	"\n  IQ80310 Hardware Tests"


PCI_DATA pci_devices = {0, 0};
extern void __reset(void);

void hdwr_diag (void)
{
unsigned char* led0 = (unsigned char*)MSB_DISPLAY_REG;
unsigned char* led1 = (unsigned char*)LSB_DISPLAY_REG;

	*led0 = LETTER_S;
	*led1 = LETTER_S;

	printf ("Entering Hardware Diagnostics - Disabling Data Cache!\n\n");

	__disableDCache();
	
	sys_pci_device_initialization (&pci_devices);

	_enableFiqIrq(); /* enable FIQ and IRQ interrupts */
	 
	config_ints();  /* configure interrupts for diagnostics */

	init_external_timer();

		/* 01/11/01 jwf */
	select_host_test_system();
	
	menu (testMenu, NUM_MENU_ITEMS, MENU_TITLE, MENU_OPT_NONE);

	printf ("Exiting Hardware Diagnostics - Reenabling Data Cache!\n\n");

	// _enableDCache(); /* reenable DCache */

	uninit_external_timer();


	*led0 = ZERO;
	*led1 = ZERO;

 	__reset();  /* reset the board so RedBoot starts with a clean slate */
}

// Use "naked" attribute to suppress C prologue/epilogue
static void __attribute__ ((naked)) _coy_tight_loop(void)
{
    asm ( "0: mov r0,r0\n"
	  "b 0b\n");
}


/* 02/02/01 jwf */
static void cache_loop (void)
{
	printf ("Putting Processor in a Tight Loop Forever...\n\n");

	_coy_tight_loop();

	/* not reached */
}


/************************************************/
/* Secondary PCI Bus Test						*/
/*												*/
/* This test assumes that a IQ80303 eval board  */
/* is installed in a secondary PCI slot. This   */
/* second board must be configured with 32 Meg  */
/* of SDRAM minimum.				            */
/*												*/
/************************************************/
static void spci_tests (void)
{
	long	start_addr;
	long	mem_size;
	long	end_addr;
	int first_ctrlr = 0; 
	PCI_DEVICE_LOCATION dev_loc;

	/* Look for ATU on the secondary PCI Bus */
	printf("\nLooking for a IQ80303 board on the Secondary PCI bus:\n");
	while (TRUE)
	{
		if (Device_Seek (FALSE, VENDOR_INTEL, I80303_ATU, first_ctrlr, &dev_loc) == OK)
		{
			if (dev_loc.bus_number != SECONDARY_BUS_NUM)
			{
				continue;
			}
			else
			{
				printf("An IQ80303 board has been detected on the Secondary PCI bus.");
				break;
			}
		}
		else
		{
			printf("No IQ80303 board detected on the SPCI bus!\n");
			return;
		}
	}

	printf ("i80303 ATU located at bus = 0x%02X, dev = 0x%02X, func = 0x%02X\n",
		dev_loc.bus_number, dev_loc.device_number, dev_loc.function_number);

	/* read the PCI address which corresponds to the start of DRAM */
	if (sys_read_config_dword (dev_loc.bus_number, dev_loc.device_number, dev_loc.function_number, 0x10, (UINT32 *)&start_addr) == ERROR)
	{
		printf ("Error reading PCI BAR for ATU\n");
		return;
	}

	/* strip off indicator bits */
	start_addr &= 0xfffffff0;

	printf ("i80303 DRAM starts at PCI address 0x%08X\n", start_addr);

	/* skip over 1st Mbyte of target DRAM */
	start_addr += 0x100000;

	mem_size = 0x1f00000;
	end_addr = start_addr + mem_size;

	printf("\n\nTesting memory from $");
	hex32out(start_addr);
	printf(" to $");
	hex32out(end_addr);
	printf(".\n");

	memTest(start_addr, end_addr);
	printf("\n");

	printf ("\nMemory test done.\n");
	printf ("Press return to continue.\n");
	(void) hexIn();
}

/************************************************/
/* Primary PCI Bus Test						    */
/*												*/
/* This test assumes that a IQ80303 eval board  */
/* is installed in a primary PCI slot. This     */
/* second board must be configured with 32 Meg  */
/* of SDRAM minimum.				            */
/*												*/
/************************************************/
static void ppci_tests (void)
{
	long	start_addr;
	long	mem_size;
	long	end_addr;
	int first_ctrlr = 0; 
	PCI_DEVICE_LOCATION dev_loc;

	/* check to see if we are the host of the backplane, if not 
	   return an error */
	if (isHost() == FALSE)
	{
		printf ("Invalid test configuration, must be PCI host!\n");
		return;
	}

	/* Look for ATU on the primary PCI Bus */
	printf("\nLooking for a IQ80303 board on the Primary PCI bus:\n");
	while (TRUE)
	{
		if (Device_Seek (FALSE, VENDOR_INTEL, I80303_ATU, first_ctrlr, &dev_loc) == OK)
		{
			if (dev_loc.bus_number != PRIMARY_BUS_NUM)
			{
				continue;
			}
			else
			{
				printf("An IQ80303 board has been detected on the Primary PCI bus\n");
				break;
			}
		}
		else
		{
			printf("No IQ80303 board detected on the PPCI bus!\n");
			return;
		}
	}

	printf ("i80303 ATU located at bus = 0x%02X, dev = 0x%02X, func = 0x%02X\n",
		dev_loc.bus_number, dev_loc.device_number, dev_loc.function_number);

	/* read the PCI address which corresponds to the start of DRAM */
	if (sys_read_config_dword (dev_loc.bus_number, dev_loc.device_number, dev_loc.function_number, 0x10, (UINT32 *)&start_addr) == ERROR)
	{
		printf ("Error reading PCI BAR for ATU\n");
		return;
	}

	/* strip off indicator bits */
	start_addr &= 0xfffffff0;

	printf ("i80303 DRAM starts at PCI address 0x%08X\n", start_addr);

	/* skip over 1st Mbyte of target DRAM */
	start_addr += 0x100000;

	mem_size = 0x1f00000;
	end_addr = start_addr + mem_size;

	printf("\n\nTesting memory from $");
	hex32out(start_addr);
	printf(" to $");
	hex32out(end_addr);
	printf(".\n");

	memTest(start_addr, end_addr);
	printf("\n");

	printf ("\nMemory test done.\n");
	printf ("Press return to continue.\n");
	(void) hexIn();
}


/*****************************************************************************
* memory_tests - Basic Memory Tests                       
*
* Memory tests can be run one of two ways - with the cache turned OFF to test
* physical memory, or with cache turned ON to test the caching
*/
static void memory_tests (void)
{
    long	start_addr;
    long	mem_size;
    long	end_addr;

	printf ("Base address of memory to test (in hex): ");
    start_addr = hexIn();
    printf("\n");
    printf ("Size of memory to test (in hex): ");
    mem_size = hexIn();
    printf("\n");
    end_addr = start_addr + mem_size;

    printf("Testing memory from $");
    hex32out(start_addr);
    printf(" to $");
    hex32out(end_addr);
    printf(".\n");
    memTest(start_addr, end_addr);
    printf("\n");

    printf ("\nMemory test done.\n");
    printf ("Press return to continue.\n");
    (void) xgetchar();
}


/*****************************************************************************
* repeat_mem_test - Repeating Memory Tests                       
*
*/
static void repeat_mem_test (void)
{
    unsigned long start_addr, mem_size, end_addr;
	char	cache_disable[10];

	printf ("Turn off Data Cache? (y/n): ");
	sgets (cache_disable);
	printf ("\n");
    printf ("Base address of memory to test (in hex): ");
    start_addr = hexIn();
    printf("\n");
    printf ("Size of memory to test (in hex): ");
    mem_size = hexIn();
    printf("\n");
    end_addr = start_addr + mem_size;
    printf("Testing memory from $");
    hex32out(start_addr);
    printf(" to $");
    hex32out(end_addr);
    while (memTest (start_addr, end_addr))
        ;
}

/* 02/02/01 jwf */
/*****************************************************************************
* special_mem_test - Repeat-On-Fail Memory Test                     
*
* Memory tests can be run one of two ways - with the cache turned OFF to test