iq80310.h

Intel XScale PXA255 引导Linux的Redboot 版bootloader源代码！

//=============================================================================
//
//      iq80310.h - Cyclone Diagnostics
//
//=============================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 2001 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   Scott Coulter, Jeff Frazier, Eric Breeden
// Contributors:
// Date:        2001-01-25
// Purpose:     
// Description: 
//
//####DESCRIPTIONEND####
//
//===========================================================================*/

/******************************************************************************/
/* iq80310.h - Header file for Cyclone IQ80310 Evaluation Board				  */
/*																			  */
/* modification history														  */
/* --------------------														  */
/* 07sep00, ejb, Written for IQ80310 Cygmon diagnostics						  */
/* 18dec00  jwf                                                               */
/* 09feb01  jwf                                                               */
/******************************************************************************/

#ifndef NULL
#define NULL ((void *)0)
#endif

#ifndef ERROR
#define ERROR -1
#endif

#ifndef OK
#define OK 0
#endif

#ifndef TRUE
#define TRUE 1
#endif

#ifndef FALSE
#define FALSE 0
#endif

#define RAM_FUNC_SECT

/* 02/09/01 jwf */
/* Specify the operating system for version information retrieval */
#define CYGNUS_CYGMON_OS			FALSE
#if CYGNUS_CYGMON_OS
	#define REDHAT_REDBOOT_OS		FALSE
#else
	#define REDHAT_REDBOOT_OS		TRUE
#endif

typedef int				STATUS;
typedef unsigned char	UCHAR;
typedef unsigned char	UINT8;
typedef unsigned short	USHORT;
typedef unsigned short	UINT16;
typedef unsigned long	ULONG;
typedef unsigned int	UINT;
typedef unsigned int	UINT32;
typedef int 			(*FUNCPTR) ();	   
typedef void 			(*VOIDFUNCPTR) (); 

/* board specific definitions */


#define MEMBASE_DRAM		0xa0000000


/* UART definitions */
#define	SCALE		   		0x10000		/* distance between port addresses */
#define	TERMINAL		   	0xfe800000	/* Terminal base address */
#define ACCESS_DELAY		5
#define DFLTPORT			0			/* channel 2 on 16C552 */
#define XTAL				1843200		/* frequency of baud rate generation crystal */

/* Backplane Detect Register */
#define BACKPLANE_DET_REG		(volatile unsigned char *)0xfe870000
#define BP_HOST_BIT				0x1 

/* PAL-based external timer definitions */
#define TIMER_LA0_REG_ADDR		(volatile unsigned char *)0xfe880000
#define TIMER_LA1_REG_ADDR		(volatile unsigned char *)0xfe890000
#define TIMER_LA2_REG_ADDR		(volatile unsigned char *)0xfe8a0000
#define TIMER_LA3_REG_ADDR		(volatile unsigned char *)0xfe8b0000
#define TIMER_ENABLE_REG_ADDR	(volatile unsigned char *)0xfe8c0000

#define TIMER_COUNT_MASK		0x5f	/* 6 bits of timer data with the MSB in bit 6 not bit 5 */
#define TIMER_CNT_ENAB			0x1
#define TIMER_INT_ENAB			0x2
#define EXT_TIMER_CLK_FREQ		33000000	/* external timer runs at 33 MHz */
#define TICKS_10MSEC			100			/* 10msec = 100 ticks/sec */
#define EXT_TIMER_10MSEC_COUNT	(EXT_TIMER_CLK_FREQ / TICKS_10MSEC)
#define TICKS_5MSEC				200			/* 5msec = 200 ticks/sec */
#define EXT_TIMER_5MSEC_COUNT	(EXT_TIMER_CLK_FREQ / TICKS_5MSEC)

#define EXT_TIMER_CNT_ENAB()		(*TIMER_ENABLE_REG_ADDR |= TIMER_CNT_ENAB)
#define EXT_TIMER_CNT_DISAB()		(*TIMER_ENABLE_REG_ADDR &= ~TIMER_CNT_ENAB)
#define EXT_TIMER_INT_ENAB()		(*TIMER_ENABLE_REG_ADDR |= TIMER_INT_ENAB)
#define EXT_TIMER_INT_DISAB()		(*TIMER_ENABLE_REG_ADDR &= ~TIMER_INT_ENAB)

/* 80312 Interrupt Status Registers */
#define X3ISR_ADDR	0xfe820000	/* XINT3 (external interrupts) Status Register */
#define X3MASK_ADDR 0xfe860000	/* XINT3 Mask Register */


/* 12/18/00 jwf */
/* CPLD Read only Registers */
#define BOARD_REV_REG_ADDR	(volatile unsigned char *)0xfe830000	/* Board Revision Register, xxxxbbbb=0x2<-->Rev B Board, Note: This was not implemented in the CPLD for board revisions A,B,C and D. */
#define BOARD_REV_E			(unsigned char)0x5						/* BOARD REV E */
#define BOARD_REV_MASK		(unsigned char)0xf						/* use only b0-b3 */
#define CPLD_REV_REG_ADDR	(volatile unsigned char *)0xfe840000	/* CPLD Revision Register, data examples: xxxxbbbb=0x3<-->Rev C CPLD(used on PCI-700 Rev D Board), xxxxbbbb=0x4<-->Rev D CPLD(used on PCI-700 Rev E Board) */
#define SINT_REG_ADDR		(volatile unsigned char *)0xfe850000	/* SINTA-SINTC secondary PCI interrupt status register */
/* SINT_REG_ADDR Register Interrupt Status bit definitions */
#define SINTA_INT			(unsigned char)0x1						/* b0=1, Secondary PCI (S_INTA) Interrupt Pending */
#define SINTB_INT			(unsigned char)0x2						/* b1=1, Secondary PCI (S_INTB) Interrupt Pending */
#define SINTC_INT			(unsigned char)0x4						/* b2=1, Secondary PCI (S_INTC) Interrupt Pending */
#define SINT_MASK			(unsigned char)0x7						/* isolate bits b0-b2 */
#define RI_MASK				(unsigned char)0x40						/* use to isolate bit 6, Ring Indicator, of MSR in UART 2 */

/* Intel 28F640J3A Strata Flash Memory Definitions */
#define NUM_FLASH_BANKS		1					/* number of flash banks, there is only 1 flash memory chip on the pci-700 board */
#define FLASH_WIDTH			1					/* width of flash in bytes */
#define FLASH_BASE_ADDR		0x00000000 			/* base address of flash block 0, avoid this area, vectors and cygmon code occupy addresses 0x2000h-0x28000h */
#define DEV_CODE_ADDR		(0x00000001 << 1)	/* address of Device Code in Flash memory, note that address bit A0 is not used, must shift 0x00000001<<1=0x00000002 */

/* 10/17/00 jwf */
#define FLASH_BLK4_BASE_ADDR		0x80000

#define FLASH_TOP_ADDR		0x7fffff			/* last address of last block of flash memory */
#define FLASH_ADDR			0x00000000 			/* base address of flash block 0, avoid this area, vectors and cygmon code occupy addresses 0x2000h-0x28000h */
#define FLASH_ADDR_INCR		0x00020000			/* address offset of each flash block, 128K block, byte-wide (X8) mode, device address range 0-7fffff */
#define VALID_FLASH_ADDR	0x00000000 			/* base address of flash block 0 */ 
#define FLASH_TIME_ADJUST	1					/* delay adjustment factor for delay times */

/* 10/17/00 jwf */
#define RESERVED_AREA1		0x0			/* 0h-1ffffh is partially occupied by Cygnus Cygmon monitor and debug code */
#define RESERVED_AREA2		0x20000		/* 20000h-3ffffh is partially occupied by Cygnus Cygmon monitor and debug code */   
#define RESERVED_AREA3		0x40000		/* 40000h-5ffffh is partially occupied by Cygnus Cygmon debug code */   
#define RESERVED_AREA4		0x60000		/* 60000h-7ffffh is partially occupied by Cygnus Cygmon debug code */   
#define RESERVED_AREA_SIZE  0x80000		/* 20000h * 4h */

/* Definitions for Battery Backup SDRAM memory test */
#define	SDRAM_BATTERY_TEST_BASE		0xA1FFFFF0		/* base address of last 16 memory locations in 32MB SDRAM */
/* #define BATTERY_TEST_PATTERN		0xBAEBAEBA */
#define BATTERY_TEST_PATTERN		0x55555555


/* 02/09/01 jwf */
/* Use a base address set to the fourth memory location from the last memory location */
/* in a 32MB SDRAM DIMM to store the 80200 Coyanosa ID 32 bit data */
#define	COYANOSA_ID_BASE_ADDR		0xA1FFFFFC

/* Definitions for data types and constants used in Flash.c */
typedef unsigned long ADDR;			
#define NO_ADDR ((ADDR)0x800000)	/* last address of Flash memory + 1 */
int cmd_stat;						
#ifndef ERR
#define ERR	-1					
#endif
/* Error code Constants */
#define	E_EEPROM_ADDR	12		
#define	E_EEPROM_PROG	13			
#define	E_EEPROM_FAIL	14		
#define E_NO_FLASH	29				


/* 10/17/00 jwf */
#define BREEZE_BLOCK_0			0x0 	
#define NUM_BREEZE_BLOCKS		  4		
#define NUM_FLASH_BLOCKS		 64	






/* 80310 IRQ Interrupt Identifiers (used for connecting and disconnecting ISRs) */
#define DMA0_INT_ID		0
#define DMA1_INT_ID		1
#define DMA2_INT_ID		2
#define PM_INT_ID		3
#define AA_INT_ID		4
#define I2C_INT_ID		5
#define MU_INT_ID		6
#define PATU_INT_ID		7	
#define TIMER_INT_ID	8
#define ENET_INT_ID		9
#define UART1_INT_ID	10
#define UART2_INT_ID	11
#define SINTA_INT_ID	12
#define SINTB_INT_ID	13
#define SINTC_INT_ID	14
#define SINTD_INT_ID	15



/* XINT3 External Interrupt Status and Mask bit definitions */
#define TIMER_INT		(1 << 0)	/* Timer Interrupt Pending */
#define ENET_INT		(1 << 1)	/* Ethernet Interrupt Pending */
#define UART1_INT		(1 << 2)	/* UART1 Interrupt Pending */
#define UART2_INT		(1 << 3)	/* UART2 Interrupt Pending */
#define SINTD_INT		(1 << 4)	/* Secondary PCI (S_INTD) Interrupt Pending */

/* XINT6 Interrupt Status bit definitions */
#define DMA0_INT		(1 << 0)	/* DMA Channel 0 Interrupt Pending */
#define DMA1_INT		(1 << 2)	/* DMA Channel 1 Interrupt Pending */
#define DMA2_INT		(1 << 3)	/* DMA Channel 2 Interrupt Pending */
#define PM_INT			(1 << 5)	/* Performance Monitoring Unit Interrupt Pending */
#define AA_INT			(1 << 6)	/* Application Accelerator Interrupt Pending */

/* XINT7 Interrupt Status bit definitions */
#define I2C_INT			(1 << 1)	/* I2C Interrupt Pending */
#define MU_INT			(1 << 2)	/* Messaging Unit Interrupt Pending */
#define PATU_INT		(1 << 3)	/* Primary ATU / BIST Start Interrupt Pending */

/* NISR bit definitions */
#define MCU_ERROR		(1 << 0)		/* 80960 core Error within internal memory controller */
#define PATU_ERROR		(1 << 1)		/* Primary ATU Error (PCI or local bus error) */
#define SATU_ERROR		(1 << 2)		/* Secondary ATU Error (PCI or local bus error) */
#define PBRIDGE_ERROR	(1 << 3)		/* Primary Bridge Interface Error */
#define SBRIDGE_ERROR	(1 << 4)		/* Secondary Bridge Interface Error */
#define DMA_0_ERROR		(1 << 5)		/* DMA Channel 0 Error (PCI or local bus error) */
#define DMA_1_ERROR		(1 << 6)		/* DMA Channel 1 Error (PCI or local bus error) */
#define DMA_2_ERROR		(1 << 7)		/* DMA Channel 2 Error (PCI or local bus error) */
#define MU_ERROR		(1 << 8)		/* Messaging Unit NMI interrupt */
#define AAU_ERROR		(1 << 10)		/* Application Accelerator Unit Error */
#define BIU_ERROR		(1 << 11)		/* Bus Interface Unit Error */



/* macros to clear (S/P PCI Status register bits) */
#define CLEAR_PATU_STATUS()		(*(volatile UINT16 *)PATUSR_ADDR |= 0xf900)
#define CLEAR_SATU_STATUS()		(*(volatile UINT16 *)SATUSR_ADDR |= 0xf900)
#define CLEAR_PBRIDGE_STATUS()	(*(volatile UINT16 *)PSR_ADDR |= 0xf900)
#define CLEAR_SBRIDGE_STATUS()	(*(volatile UINT16 *)SSR_ADDR |= 0xf900)