📄 hal_arm_iq80310.cdl
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# ====================================================================## hal_arm_iq80310.cdl## IQ80310 evaluation board HAL package configuration data## ====================================================================#####COPYRIGHTBEGIN##### # ------------------------------------------- # The contents of this file are subject to the Red Hat eCos Public License # Version 1.1 (the "License"); you may not use this file except in # compliance with the License. You may obtain a copy of the License at # http://www.redhat.com/ # # Software distributed under the License is distributed on an "AS IS" # basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the # License for the specific language governing rights and limitations under # the License. # # The Original Code is eCos - Embedded Configurable Operating System, # released September 30, 1998. # # The Initial Developer of the Original Code is Red Hat. # Portions created by Red Hat are # Copyright (C) 1998, 1999, 2000 Red Hat, Inc. # All Rights Reserved. # ------------------------------------------- # #####COPYRIGHTEND##### ====================================================================######DESCRIPTIONBEGIN###### Author(s): msalter# Original data: # Contributors:# Date: 2000-10-09######DESCRIPTIONEND###### ====================================================================cdl_package CYGPKG_HAL_ARM_IQ80310 { display "Intel IQ80310 XScale evaluation boards" parent CYGPKG_HAL_ARM define_header hal_arm_iq80310.h include_dir cyg/hal hardware description " The IQ80310 HAL package provides the support needed to run eCos on an Intel IQ80310 XScale eval board." compile hal_diag.c iq80310_misc.c iq80310_pci.c implements CYGINT_HAL_DEBUG_GDB_STUBS implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT define_proc { puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>" puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_iq80310.h>" puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_IO_H <cyg/hal/plf_io.h>" puts $::cdl_header "#define HAL_PLATFORM_CPU \"XScale\"" puts $::cdl_header "#define HAL_PLATFORM_BOARD \"IQ80310\"" puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\"" puts $::cdl_header "#define HAL_REDBOOT_VERSION \"1.00\"" puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK iq80310_program_new_stack" } cdl_component CYG_HAL_STARTUP { display "Startup type" flavor data default_value {"RAM"} legal_values {"RAM" "ROM"} no_define define -file system.h CYG_HAL_STARTUP description " When targetting the IQ80310 eval board it is possible to build the system for either RAM bootstrap or ROM bootstrap(s). Select 'ram' when building programs to load into RAM using onboard debug software such as Angel or eCos GDB stubs. Select 'rom' when building a stand-alone application which will be put into ROM. Selection of 'stubs' is for the special case of building the eCos GDB stubs themselves." } cdl_option CYGSEM_HAL_ARM_IQ80310_ARMBOOT { display "Coexist with ARM bootloader" flavor bool default_value 0 description " Enable this option if the ARM bootloader is programmed into the FLASH boot sector on the board." } cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT { display "Default console channel." flavor data legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 calculated 0 } cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { display "Number of communication channels on the board" flavor data calculated 2 } cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { display "Debug serial port" flavor data legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 default_value 0 description " This option chooses which port will be used to connect to a host running GDB." } cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { display "Diagnostic serial port" flavor data legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 default_value 0 description " The EBSA285 board has only one serial port. This option chooses which port will be used for diagnostic output." } cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { display "Diagnostic serial port baud rate" flavor data legal_values 9600 19200 38400 57600 115200 default_value 115200 description " This option selects the baud rate used for the diagnostic port. Note: this should match the value chosen for the GDB port if the diagnostic and GDB port are the same." } cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { display "GDB serial port baud rate" flavor data legal_values 9600 19200 38400 57600 115200 default_value 115200 description " This option selects the baud rate used for the GDB port." } # Real-time clock/counter specifics cdl_component CYGNUM_HAL_RTC_CONSTANTS { display "Real-time clock constants" flavor none cdl_option CYGNUM_HAL_RTC_NUMERATOR { display "Real-time clock numerator" flavor data calculated 1000000000 } cdl_option CYGNUM_HAL_RTC_DENOMINATOR { display "Real-time clock denominator" flavor data calculated 100 } cdl_option CYGNUM_HAL_RTC_PERIOD { display "Real-time clock period" flavor data calculated 330000 ;# External timer is 33MHz } } cdl_component CYGBLD_GLOBAL_OPTIONS { display "Global build options" flavor none description " Global build options including control over compiler flags, linker flags and choice of toolchain." parent CYGPKG_NONE cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { display "Global command prefix" flavor data no_define default_value { "xscale-elf" } description " This option specifies the command prefix used when invoking the build tools." } cdl_option CYGBLD_GLOBAL_CFLAGS { display "Global compiler flags" flavor data no_define
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