sa2sim_misc.c

Intel XScale PXA255 引导Linux的Redboot 版bootloader源代码！

//==========================================================================
//
//      sa2sim_misc.c
//
//      HAL misc board support code for Coyanosa (StrongARM II) sim.
//
//==========================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    hmt
// Contributors: hmt
// Date:         2000-02-14
// Purpose:      HAL board support
// Description:  Implementations of HAL board interfaces
//
//####DESCRIPTIONEND####
//
//========================================================================*/

#include <pkgconf/hal.h>
#include <pkgconf/system.h>
#include CYGBLD_HAL_PLATFORM_H

#include <cyg/infra/cyg_type.h>         // base types
#include <cyg/infra/cyg_trac.h>         // tracing macros
#include <cyg/infra/cyg_ass.h>          // assertion macros

#include <cyg/hal/hal_io.h>             // IO macros
#include <cyg/hal/hal_arch.h>           // Register state info
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_intr.h>           // Interrupt names
#include <cyg/hal/hal_cache.h>
#include <cyg/hal/hal_sa2.h>            // Hardware definitions

#include <cyg/infra/diag.h>             // diag_printf


static void
hal_bsp_mmu_init(int sdram_size);

// Some initialization has already been done before we get here.
//
// Set up the MMU so that we can use caches.
// Enable caches.
// - All done!


void hal_hardware_init(void)
{
    if ( 0 == hal_dram_size || 0 != (0xfffff & hal_dram_size) )
        hal_dram_size = SZ_64M; /* pick a number... 64Mb should do */

    // Set up MMU so that we can use caches
    hal_bsp_mmu_init( hal_dram_size );

    // Enable caches
    HAL_DCACHE_ENABLE();
    HAL_ICACHE_ENABLE();
}

// -------------------------------------------------------------------------
// MMU initialization:

static void
hal_bsp_mmu_init(int sdram_size)
{
    unsigned long ttb_base = ((unsigned long)0x4000); // could be external
    unsigned long i;


    /*
     * Set the TTB register
     */
    asm volatile ("mcr  p15,0,%0,c2,c0,0" 
                  :
                  : "r"(ttb_base)
                /*:*/
        );
    /*
     * Set the Domain Access Control Register
     */
    i = ARM_ACCESS_TYPE_MANAGER(0)    | 
        ARM_ACCESS_TYPE_NO_ACCESS(1)  |
        ARM_ACCESS_TYPE_NO_ACCESS(2)  |
        ARM_ACCESS_TYPE_NO_ACCESS(3)  |
        ARM_ACCESS_TYPE_NO_ACCESS(4)  |
        ARM_ACCESS_TYPE_NO_ACCESS(5)  |
        ARM_ACCESS_TYPE_NO_ACCESS(6)  |
        ARM_ACCESS_TYPE_NO_ACCESS(7)  |
        ARM_ACCESS_TYPE_NO_ACCESS(8)  |
        ARM_ACCESS_TYPE_NO_ACCESS(9)  |
        ARM_ACCESS_TYPE_NO_ACCESS(10) |
        ARM_ACCESS_TYPE_NO_ACCESS(11) |
        ARM_ACCESS_TYPE_NO_ACCESS(12) |
        ARM_ACCESS_TYPE_NO_ACCESS(13) |
        ARM_ACCESS_TYPE_NO_ACCESS(14) |
        ARM_ACCESS_TYPE_NO_ACCESS(15);

    asm volatile ("mcr  p15,0,%0,c3,c0,0" 
                  :
                  : "r"(i)
                /*:*/
        );

    /*
     * First clear all TT entries - ie Set them to Faulting
     */
    memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);

    /*
     * We only do direct mapping for the sa2simulator. That is, all
     * virt_addr == phys_addr.
     */

    /*
     * Actual Base = 0x000(00000)
     * Virtual Base = 0x000(00000)
     * Size = Max SDRAM
     * SDRAM
     */
    for (i = 0x000; i < (sdram_size >> 20); i++) {
        ARM_MMU_SECTION(ttb_base, i, i,
                        ARM_MMU_SECTION_CACHE_WRITEBACK,
                        ARM_ACCESS_PERM_RW_RW, ARM_ACCESS_NO_ECC );
    }

    /*
     * Actual Base = 0xf00(00000)-0xf00(FFFFF)
     * Virtual Base = 0xf00(00000)-0xf00(FFFFF)
     * Size = 1M
     * Nonexistent, cachable (Cache Clean) Bank.
     * Read only.
     */
    for (i = 0xf00; i <= 0xf00; i++) {
        ARM_MMU_SECTION(ttb_base, i, i,
                        ARM_MMU_SECTION_CACHE_WRITEBACK,
                        ARM_ACCESS_PERM_RO_RO, ARM_ACCESS_NO_ECC );
    }

    /*
     * Actual Base = 0xf01(00000)-0xf01(FFFFF)
     * Virtual Base = 0xf01(00000)-0xf01(FFFFF)
     * Size = 1M
     * Nonexistent, cachable (Cache Clean) Bank
     * for the mini data cache.  Read only.
     */
    for (i = 0xf01; i <= 0xf01; i++) {
        ARM_MMU_SECTION(ttb_base, i, i,
                        ARM_MMU_SECTION_MINIDATACACHE,
                        ARM_ACCESS_PERM_RO_RO, ARM_ACCESS_NO_ECC );
    }


}

// -------------------------------------------------------------------------
#if CYGNUM_HAL_INTERRUPT_RTC == CYGNUM_HAL_INTERRUPT_NIRQ
// Old version that requires bangirq, to, um, bang away.

static cyg_uint32 _period;

void hal_clock_initialize(cyg_uint32 period)
{
    _period = period;
    // That's all.
}

// This routine is called during a clock interrupt.

void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
{
    // nothing!
}

// Read the current value of the clock, returning the number of hardware
// "ticks" that have occurred (i.e. how far away the current value is from
// the start)

void hal_clock_read(cyg_uint32 *pvalue)
{
    *pvalue = (cyg_uint32)(_period / 2); // Utter nonsense.
}

#else
// Proper version that uses the clock counter in the PMU to do proper
// interrupts that require acknowledgement and all that good stuff.

static cyg_uint32 hal_clock_init_period; // The START value, it counts up

void hal_clock_initialize(cyg_uint32 period)
{
    // event types both zero; clear all 3 interrupts;
    // disable all 3 counter interrupts;
    // CCNT counts every processor cycle; reset all counters;
    // enable PMU.
    register cyg_uint32 init = 0x00000707;
    asm volatile (
        "mcr      p14,0,%0,c0,c0,0;" // write into PMNC
        :
        : "r"(init)
        /*:*/
        );
    // the CCNT in the PMU counts *up* then interrupts at overflow
    // ie. at 0x1_0000_0000 as it were.
    // So init to 0xffffffff - period + 1 to get the right answer.
    period = (~period) + 1;
    hal_clock_init_period = period;
    hal_clock_reset( 0, 0 );
}

// This routine is called during a clock interrupt.
// (before acknowledging the interrupt)
void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
{
    asm volatile (
        "mrc      p14,0,r0,c1,c0,0;" // read from CCNT - how long since OVFL
        "add      %0, %0, r0;"       // synchronize with previous overflow
        "mcr      p14,0,%0,c1,c0,0;" // write into CCNT
        :
        : "r"(hal_clock_init_period)
        : "r0"
        );
}