📄 hal_platform_ints.h
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#ifndef CYGONCE_HAL_PLATFORM_INTS_H#define CYGONCE_HAL_PLATFORM_INTS_H//==========================================================================//// hal_platform_ints.h//// HAL Interrupt and clock support////==========================================================================//####COPYRIGHTBEGIN####// // ------------------------------------------- // The contents of this file are subject to the Red Hat eCos Public License // Version 1.1 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://www.redhat.com/ // // Software distributed under the License is distributed on an "AS IS" // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the // License for the specific language governing rights and limitations under // the License. // // The Original Code is eCos - Embedded Configurable Operating System, // released September 30, 1998. // // The Initial Developer of the Original Code is Red Hat. // Portions created by Red Hat are // Copyright (C) 1998, 1999, 2000 Red Hat, Inc. // All Rights Reserved. // ------------------------------------------- // //####COPYRIGHTEND####//==========================================================================//#####DESCRIPTIONBEGIN####//// Author(s): hmt// Contributors: hmt// Date: 2000-02-14// Purpose: Define Interrupt support// Description: The interrupt details for the Coyanosa (StrongARM II)// simulator are defined here. There's not much to it.// Usage:// #include <cyg/hal/hal_platform_ints.h>// ...// ////####DESCRIPTIONEND####////==========================================================================#define CYGNUM_HAL_INTERRUPT_reserved0 0#define CYGNUM_HAL_INTERRUPT_PMU_PMN0_OVFL 1 // See Ch.12 - Performance Mon.#define CYGNUM_HAL_INTERRUPT_PMU_PMN1_OVFL 2 // PMU counter 0/1 overflow#define CYGNUM_HAL_INTERRUPT_PMU_CCNT_OVFL 3 // PMU clock overflow#define CYGNUM_HAL_INTERRUPT_BCU_INTERRUPT 4 // See Ch.11 - Bus Control Unit#define CYGNUM_HAL_INTERRUPT_NIRQ 5 // external IRQ#define CYGNUM_HAL_INTERRUPT_NFIQ 6 // external FIQ#define CYGNUM_HAL_ISR_MIN 0#define CYGNUM_HAL_ISR_MAX 6// Using FIQ via an ISR will probably not work, but the interrupt API can// be used to mask, unmask and detect it. Best only to use with VSR.#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)// The vector used by the Real time clock//#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_NIRQ#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_PMU_CCNT_OVFL// ----------------------------------------------------------------------// sa2sim has a trick operation to halt the sim. With luck, this should// save a lot of time.#define CYGHWR_TEST_PROGRAM_EXIT() \CYG_MACRO_START \ asm volatile ( \ "mov r0, #0x18;" /* SYS_EXIT */ \ ".word 0xE7DEAD1A;" /* magic op SWI emulation in CoySim */ \ /* "swi 0x123456;" */ \ : \ : \ : "r0" \ ); \CYG_MACRO_END#endif // CYGONCE_HAL_PLATFORM_INTS_H
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