hal_sa2.h

Intel XScale PXA255 引导Linux的Redboot 版bootloader源代码！

#ifndef CYGONCE_HAL_SA2_H
#define CYGONCE_HAL_SA2_H

/*=============================================================================
//
//      hal_sa2.h
//
//      HAL Description of SA-110 and 21285 control registers
//      and ARM memory control in general.
//
//=============================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    hmt
// Contributors: hmt
// Date:         2000-02-14
// Purpose:      Intel SA2 hardware description
// Description:
// Usage:        #include <cyg/hal/hal_sa2.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/

// Note: these defintions match the documentation, thus no attempt is made
// to mangle the names against namespace pollution.  Also, care should be
// taken to keep this clean for use in assembly code (no "C" constructs).


#define SZ_1K           0x00000400
#define SZ_2K           0x00000800
#define SZ_4K           0x00001000
#define SZ_8K           0x00002000
#define SZ_16K          0x00004000
#define SZ_32K          0x00008000
#define SZ_64K          0x00010000
#define SZ_128K         0x00020000
#define SZ_256K         0x00040000
#define SZ_512K         0x00080000
#define SZ_1M           0x00100000
#define SZ_2M           0x00200000
#define SZ_4M           0x00400000
#define SZ_8M           0x00800000
#define SZ_16M          0x01000000
#define SZ_32M          0x02000000
#define SZ_64M          0x04000000
#define SZ_128M         0x08000000
#define SZ_256M         0x10000000
#define SZ_512M         0x20000000
#define SZ_1G           0x40000000

#ifdef __ASSEMBLER__

#define REG8_VAL(a)  (a)
#define REG16_VAL(a) (a)
#define REG32_VAL(a) (a)

#define REG8_PTR(a)  (a)
#define REG16_PTR(a) (a)
#define REG32_PTR(a) (a)

#else /* __ASSEMBLER__ */

#define REG8_VAL(a)  ((unsigned char)(a))
#define REG16_VAL(a) ((unsigned short)(a))
#define REG32_VAL(a) ((unsigned int)(a))

#define REG8_PTR(a)  ((volatile unsigned char *)(a))
#define REG16_PTR(a) ((volatile unsigned long *)(a))
#define REG32_PTR(a) ((volatile unsigned long *)(a))

#endif /* __ASSEMBLER__ */

#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE          SZ_16K
#define SA110_TRANSLATION_TABLE_MASK             0xFFFFC000

/*
 * SA-110 Domain Access Control Bit Masks
 */
#define SA110_DOMAIN_0_MASK                      0x00000003
#define SA110_DOMAIN_1_MASK                      0x0000000C
#define SA110_DOMAIN_2_MASK                      0x00000030
#define SA110_DOMAIN_3_MASK                      0x000000C0
#define SA110_DOMAIN_4_MASK                      0x00000300
#define SA110_DOMAIN_5_MASK                      0x00000C00
#define SA110_DOMAIN_6_MASK                      0x00003000
#define SA110_DOMAIN_7_MASK                      0x0000C000
#define SA110_DOMAIN_8_MASK                      0x00030000
#define SA110_DOMAIN_9_MASK                      0x000C0000
#define SA110_DOMAIN_10_MASK                     0x00300000
#define SA110_DOMAIN_11_MASK                     0x00C00000
#define SA110_DOMAIN_12_MASK                     0x03000000
#define SA110_DOMAIN_13_MASK                     0x0C000000
#define SA110_DOMAIN_14_MASK                     0x30000000
#define SA110_DOMAIN_15_MASK                     0xC0000000

/*
 * SA-110 Fault Status Bit Masks
 */
#define SA110_FAULT_STATUS_MASK                  0x0000000F
#define SA110_DOMAIN_MASK                        0x000000F0


// -------------------------------------------------------------------------
// MMU initialization:
// 
// These structures are laid down in memory to define the translation
// table.  For usage, see the memory setup in sa2_misc.c in this
// component.  hal_bsp_mmu_init()
// 

/*
 * SA-1100 Translation Table Base Bit Masks */
#define ARM_TRANSLATION_TABLE_MASK               0xFFFFC000

/*
 * SA-1100 Domain Access Control Bit Masks
 */
#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num)    (0x0 << (domain_num)*2)
#define ARM_ACCESS_TYPE_CLIENT(domain_num)       (0x1 << (domain_num)*2)
#define ARM_ACCESS_TYPE_MANAGER(domain_num)      (0x3 << (domain_num)*2)

// These are only useful in C, so:
#ifndef  __ASSEMBLER__

struct ARM_MMU_FIRST_LEVEL_FAULT {
    int id : 2;
    int sbz : 30;
};
#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0

struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
    int id : 2;
    int imp : 2;
    int domain : 4;
    int sbz : 1;
    int base_address : 23;
};
#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1

struct ARM_MMU_FIRST_LEVEL_SECTION {
    int id : 2;
    int xcb : 3;
    int domain : 4;
    int p : 1;
    int ap : 2;
    int sbz1 : 8;
    int base_address : 12;
};
#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2

struct ARM_MMU_FIRST_LEVEL_RESERVED {
    int id : 2;
    int sbz : 30;
};
#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3

#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
   (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))

// use these in the mode field of ARM_MMU_SECTON() to set bits X C B
#define ARM_MMU_SECTION_NOCACHE_NOWRITEBUFFER_STALL     (0) // 0 0 0
#define ARM_MMU_SECTION_NOCACHE_WRITEBUFFER             (1) // 0 0 1
#define ARM_MMU_SECTION_CACHE_WRITETHROUGH              (2) // 0 1 0
#define ARM_MMU_SECTION_CACHE_WRITEBACK                 (3) // 0 1 1 : usual
#define ARM_MMU_SECTION_DO_NOT_USE                      (4) // 1 0 0
#define ARM_MMU_SECTION_NOCACHE_WRITEBUFFER_NOCOALESCE  (5) // 1 0 1
#define ARM_MMU_SECTION_MINIDATACACHE                   (6) // 1 1 0 : mini
#define ARM_MMU_SECTION_CACHE_WRITEBACK_WRITEALLOC      (7) // 1 1 1

#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base,              \
                        mode, perm, protect)                              \
    CYG_MACRO_START                                                       \
        register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc;               \
                                                                          \
        desc.word = 0;                                                    \
        desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID;                 \
        desc.section.xcb = (mode);                                        \
        desc.section.domain = 0;                                          \
        desc.section.p = (protect);                                       \
        desc.section.ap = (perm);                                         \
        desc.section.base_address = (actual_base);                        \
        *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
                            = desc.word;                                  \
    CYG_MACRO_END

union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
    unsigned long word;
    struct ARM_MMU_FIRST_LEVEL_FAULT fault;
    struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
    struct ARM_MMU_FIRST_LEVEL_SECTION section;
    struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
};

#endif /* __ASSEMBLER__ */

#define ARM_ACCESS_NO_ECC                       0
#define ARM_ACCESS_ECC_PROTECT                  1


#define ARM_ACCESS_PERM_NONE_NONE               0
#define ARM_ACCESS_PERM_RO_NONE                 0
#define ARM_ACCESS_PERM_RO_RO                   0
#define ARM_ACCESS_PERM_RW_NONE                 1
#define ARM_ACCESS_PERM_RW_RO                   2
#define ARM_ACCESS_PERM_RW_RW                   3


/*---------------------------------------------------------------------------*/
/* end of hal_sa2.h                                                         */
#endif /* CYGONCE_HAL_SA2_H */