hal_platform_setup.h

Intel XScale PXA255 引导Linux的Redboot 版bootloader源代码！

#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
#define CYGONCE_HAL_PLATFORM_SETUP_H

/*=============================================================================
//
//      hal_platform_setup.h
//
//      Platform specific support for HAL (assembly code)
//
//=============================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    hmt
// Contributors: hmt
// Date:         2000-02-14
// Purpose:      Intel SA2 sim platform specific support routines
// Description: 
// Usage:       #include <cyg/hal/hal_platform_setup.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/

#include <pkgconf/system.h>             // System-wide configuration info
#include CYGBLD_HAL_PLATFORM_H          // Platform specific configuration
#include <cyg/hal/hal_sa2.h>            // Platform hardware definitions
#include <cyg/hal/hal_mmu.h>            // MMU definitions

// Note that we do NOT define CYGHWR_HAL_ARM_HAS_MMU so that at reset we
// jump straight into the ROM; this makes it unnecessary to take any
// special steps to switch from executing in the ROM alias at low
// addresses.  Make no difference for RAM start.


// The main useful output of this file is PLATFORM_SETUP1: it invokes lots
// of other stuff (may depend on RAM or ROM start).  The other stuff is
// divided into further macros to make it easier to manage what's enabled
// when.

#define PLATFORM_SETUP1                         \
        /* CLOCK_SWITCH */                      \
        ENABLE_COPROCESSOR_ACCESS               \
        /* DISABLE_DEBUG_UNIT */                \
        FLUSH_DISABLE_CACHES_BTB                \
        INIT_MINI_DATA_CACHE                    \
        /* INIT_PMU */                          \
        INIT_BCU                                \
        INIT_INTERRUPT_CONTROL


// Discard and disable all caches: we are about to be writing vectors...
#define FLUSH_DISABLE_CACHES_BTB                                     \
        /* flush and disable the caches and branch target buffer */ ;\
        mrc     p15,0,r1,c1,c0,0                                    ;\
        bic     r1,r1,#0x1800   /* ICache off */                    ;\
        bic     r1,r1,#0x0005   /* DCache off and MM off */         ;\
        mcr     p15,0,r1,c1,c0,0                                    ;\
        mov     r1, #0                                              ;\
        mcr     p15,0,r1,c7,c6,0 /* DCache invalidate (discard) */  ;\
        mcr     p15,0,r1,c7,c5,0 /* ICache invalidate */            ;\
        mcr     p15,0,r1,c8,c6,0 /* DCache TLB invalidate */        ;\
        mcr     p15,0,r1,c8,c5,0 /* ICache TLB invalidate */        ;\
        /* be sure invalidate "takes" before doing owt else */       \
        mrc  p15,0,r1,c2,c0,0                                       ;\
        mov  r1, r1                                                 ;\
        sub  pc, pc, #4                                             ;


#define INIT_MINI_DATA_CACHE                                         \
        mov	r0, #0 /* Write back, no write allocation */        ;\
        mcr     p15,0,r1,c1,c0,1 /* write auxiliary control reg */  ;


// Allow clock switching: very early in the startup
#define CLOCK_SWITCH                                                     \
        mov     r0, #7 /* fast as possible; multiplier is 9 */          ;\
        mcr     p14,0,r0,c6,c0,0 /* change gear and wait for PLL lock */;


#define DISABLE_DEBUG_UNIT                               \
        mov	r0, #0 /* disable */                    ;\
        mcr	p14,0,r0,c10,c0,0 /* write into cp */   ;


#define INIT_PMU                                                     \
        mov	r0, #0x000700 /* clear event bits */                ;\
        orr     r0, r0, #0x06 /* reset counters and disable all */  ;\
        mcr	p14,0,r0,c0,c0,0                                    ;


#define INIT_BCU                                        \
        mov	r0, #0x70000000 /* clear state bits */ ;\
        mcr	p13,0,r0,c0,c1,0 /* write to BCUCTL */ ;



#define INIT_INTERRUPT_CONTROL                           \
        mov	r0, #0 /* enable no sources */          ;\
        mcr	p13,0,r0,c0,c0,0 /* write to INTCTL */  ;\
        /* Steer both BCU and PMU to IRQ */              \
        mcr	p13,0,r0,c8,c0,0 /* write to INTSTR */  ;


#define ENABLE_COPROCESSOR_ACCESS                                          \
        mov	r0, # 1<<13                                               ;\
        orr	r0, r0, # 1<<0    /* enable CP0 and CP13 */               ;\
        mcr	p15,0,r0,c15,c0,1 /* write coprocessor access register */ ;


/*---------------------------------------------------------------------------*/
/* end of hal_platform_setup.h                                               */
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */