hal_cache.h

Intel XScale PXA255 引导Linux的Redboot 版bootloader源代码！

#ifndef CYGONCE_HAL_CACHE_H
#define CYGONCE_HAL_CACHE_H

//======================================================================
//
//      hal_cache.h
//
//      HAL cache control API
//
//======================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//======================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    hmt
// Contributors: hmt
// Date:         2000-02-14
// Purpose:      Cache control API
// Description:  The macros defined here provide the HAL APIs for handling
//               cache control operations.
// Usage:
//               #include <cyg/hal/hal_cache.h>
//               ...
//              
//
//####DESCRIPTIONEND####
//
//======================================================================

#include <cyg/infra/cyg_type.h>
//#include <cyg/hal/hal_mmu.h>

//----------------------------------------------------------------------
// Cache dimensions

#define HAL_DCACHE_SIZE                 0x8000 // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE            32     // Size of a data cache line
#define HAL_DCACHE_WAYS                 32     // Associativity of the cache
#define HAL_DCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))

#define HAL_ICACHE_SIZE                 0x8000 // Size of instruction cache in bytes
#define HAL_ICACHE_LINE_SIZE            32     // Size of ins cache line
#define HAL_ICACHE_WAYS                 32     // Associativity of the cache
#define HAL_ICACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))

//----------------------------------------------------------------------
// Wait for cache operation to complete - Coyanosa ISA special feature
// defined in the manual as the correct way to wait for cache ops.
// This is called "CPWAIT" in the manual.
#define HAL_CACHE_WAIT_FOR_COMPLETION()                                 \
CYG_MACRO_START                                                         \
    asm volatile (                                                      \
        "mrc  p15,0,r1,c2,c0,0;"        /* Any read of CP15 */          \
        "mov  r1, r1;"                  /* wait for data */             \
        "sub  pc, pc, #4;"              /* branch to next instr */      \
        :                                                               \
        :                                                               \
        : "r1" /* Clobber list */                                       \
        );                                                              \
CYG_MACRO_END

#define HAL_CACHE_CPWAIT() HAL_CACHE_WAIT_FOR_COMPLETION()

//----------------------------------------------------------------------
// Global control of data cache

// Enable the data cache
#define HAL_DCACHE_ENABLE()                                             \
CYG_MACRO_START                                                         \
    /* Coyanosa manual states that the control reg is read-write */     \
    asm volatile (                                                      \
        "mrc  p15,0,r1,c1,c0,0;"                                        \
        "orr  r1,r1,#0x0007;" /* ensure MM is enabled */                \
        "mcr  p15,0,r1,c1,c0,0"                                         \
        :                                                               \
        :                                                               \
        : "r1" /* Clobber list */                                       \
        );                                                              \
    HAL_CACHE_CPWAIT();                                                 \
CYG_MACRO_END

// Disable the data cache (and invalidate it, required semanitcs)
#define HAL_DCACHE_DISABLE()                                            \
CYG_MACRO_START                                                         \
    /* Coyanosa manual states that the control reg is read-write */     \
    asm volatile (                                                      \
        "mrc  p15,0,r1,c1,c0,0;"                                        \
        "bic  r1,r1,#0x0004;" /* but leave MM alone */                  \
        "mcr  p15,0,r1,c1,c0,0;"                                        \
        "mov    r1, #0;"                                                \
        "mcr    p15,0,r1,c7,c6,0" /* clear data cache */                \
        :                                                               \
        :                                                               \
        : "r1" /* Clobber list */                                       \
        );                                                              \
    HAL_CACHE_CPWAIT();                                                 \
CYG_MACRO_END

// Invalidate the entire cache (and both TLBs, just in case)
#define HAL_DCACHE_INVALIDATE_ALL()                                     \
CYG_MACRO_START                                                         \
    /* this macro can discard dirty cache lines. */                     \
    asm volatile (                                                      \
        "mov    r1, #0;"                                                \
        "mcr    p15,0,r1,c7,c6,0;"  /* clear data cache */              \
        "mcr    p15,0,r1,c8,c7,0;"  /* flush I+D TLBs */                \
        :                                                               \
        :                                                               \
        : "r1" /* Clobber list */                                       \
        );                                                              \
    HAL_CACHE_CPWAIT();                                                 \
CYG_MACRO_END
     

// Synchronize the contents of the cache with memory.
#define HAL_DCACHE_SYNC()                                               \
CYG_MACRO_START                                                         \
    /* This is slightly naff in that the only way to force a dirty */   \
    /* line out is by loading other data into its slot, so         */   \
    /* invalidating that slot.                                     */   \
    asm volatile (                                                      \
        "mov    r0, #0xf0000000;" /* my cache flush region */           \
        "add    r1, r0, #0x8000;" /* non-existent but mapped */         \
 "667: "                          /* We zero 32kB of it */              \
        "mcr    p15,0,r0,c7,c2,5;" /* Special preload-with- */          \
        "add    r0, r0, #32;"      /* -zero coyanosa op.    */          \
        "teq    r1, r0;"                                                \
        "bne    667b;"                                                  \
        /* now do the same for the mini-data-cache */                   \
        "mov    r0,   #0xf0000000;"                                     \
        "add    r0, r0, #0x100000;" /* my mini-datacache flush */       \
        "add    r1, r0, #0x0800;"  /* region: non-existent but mapped */\
 "668: "                          /* We zero 2kB of it */               \
        "mcr    p15,0,r0,c7,c2,5;" /* Special preload-with- */          \
        "add    r0, r0, #32;"      /* -zero coyanosa op.    */          \
        "teq    r1, r0;"                                                \
        "bne    668b;"                                                  \
        "mov    r0, #0;"                                                \
        "mcr    p15,0,r0,c7,c6,0;"  /* clear data cache */              \
        "mcr    p15,0,r0,c7,c10,4;" /* and drain the write buffer */    \
        :                                                               \
        :                                                               \
        : "r0","r1" /* Clobber list */                                  \
        );                                                              \
    HAL_CACHE_CPWAIT();                                                 \
CYG_MACRO_END

// Query the state of the data cache
#define HAL_DCACHE_IS_ENABLED(_state_)                                  \
CYG_MACRO_START                                                         \
    /* Coyanosa manual says that the control reg is readable */         \
    register int reg;                                                   \
    asm volatile ("mrc  p15,0,%0,c1,c0,0"                               \
                  : "=r"(reg)                                           \
                  :                                                     \
                /*:*/                                                   \
        );                                                              \
    (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */          \
CYG_MACRO_END

// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)