cpu.pil

Intel XScale PXA255 引导Linux的Redboot 版bootloader源代码！

print "\n========= Simulation Starts =========\n";
print "Simulator CPU Version = ";
print cpu.version;
print "\n\n";

//cpu.ex.trace.enable=1;  // Disassembly as we go along.

cpu.ex.syscall.enable=1;  // Enable the 0xE7DEAD1A opcode to do printfs!

//cpu.ex.debug.enable=1;  // Only for angel debugger

// ----------------------------------------------------------------------
// example routines for very verbose output

//cpu.cycle{
//print"------------- Cycle: "; print cpu.cycle; print" ----------------\n";
//print "R0 = "; printx cpu.byp.R0; print "\n";
//print "R2 = "; printx cpu.byp.R2; print "\n";
//print "R14 = "; printx cpu.byp.R14; print "\n";
//print "CPSR = "; printx cpu.ex.CPSR; print "\n";
//print "SPSR_FIQ = "; printx cpu.ex.SPSR_FIQ; print "\n";
//print "PC = "; printx cpu.ex.pc; print "\n";
//}

//cpu.cycle{
//    print "------------- Cycle: ";
//    print cpu.cycle;
//    print" ----------------\n";
//}

// cpu.cycle{
//     print"------------- Cycle: "; print cpu.cycle; print" ----------------\n";
//     print "R0 = "; printx cpu.byp.R0; print "\n";
//     print "R1 = "; printx cpu.byp.R1; print "\n";
//     print "CPSR = "; printx cpu.ex.CPSR; print "\n";
// }


// ----------------------------------------------------------------------
// CPU log configuration and exception actions:
log_swi = 1;                            // SWIs per se
log_emulated_swi = 0;                   // the 0xE7DEAD1A "trap"
log_irq = 0;                            // IRQs

log_registers = 0;                      // registers at each instruction

halt_on_abort = 1;                      // HALT if a DATA ABORT occurs
halt_on_prefetchabort = 1;              // HALT if a PREFETCH ABORT occurs
halt_on_undef_instruction = 1;          // HALT if UNDEFINED INSTRUCTION trap

// ----------------------------------------------------------------------
// Confirm correct application exit
cpu.programexit {
    print "\n\n-------------------------------------\n";
    print "Safe Application exit at Cycle ";
    print cpu.cycle;
    print "\nPC = "; printx cpu.ex.pc;
    print " R14 = "; printx cpu.byp.R14;
    print " CPSR = "; printx cpu.ex.CPSR;
    print "\n";
    print "========== Simulation Ends ==========\n\n";
    exit 0;
}

// ----------------------------------------------------------------------
// Check what to log per instruction retirement:
cpu.ex.retireInst {

    if ( log_registers ) {
        print "Cycle: "; print cpu.cycle;
        print " R0 = "; printx cpu.byp.R0;
        print " R1 = "; printx cpu.byp.R1;
        print " R2 = "; printx cpu.byp.R2;
        print " R3 = "; printx cpu.byp.R3;
        print " CPSR = "; printx cpu.ex.CPSR; print "\n";
    }

    if ( log_emulated_swi && (0xdeadcafe == cpu.ex.pc) ) {
        print "---------------------------------------------------------\n";
        print "---------- <emulated SWI instruction - bad op>-----------\n";
        print "Cycle: "; print cpu.cycle;
        print " R0 = "; printx cpu.byp.R0;
        print " R1 = "; printx cpu.byp.R1;
        print " R2 = "; printx cpu.byp.R2;
        print " R3 = "; printx cpu.byp.R3;
        print " CPSR = "; printx cpu.ex.CPSR; print "\n";
    }

    if ( 0x0 == cpu.ex.pc ) {
        // Reset - SVC mode
        print "------ Cycle: "; print cpu.cycle; print" ------\n";
        print "***RESET  ";
	print " LR = "; printx cpu.byp.R14_SVC;
	print " CPSR = "; printx cpu.ex.CPSR;
	print " SPSR = "; printx cpu.ex.SPSR_SVC;
        print "\n";
    }
    if ( 0x4 == cpu.ex.pc ) {
        // ***UNDEFINED INSTRUCTION*** UNDEF mode
        print "------ Cycle: "; print cpu.cycle; print" ------\n";
        print "***UNDEFINED INSTRUCTION***";
	print " LR = "; printx cpu.byp.R14_UNDEF;
	print " CPSR = "; printx cpu.ex.CPSR;
	print " SPSR = "; printx cpu.ex.SPSR_UNDEF;
        print "\n";
        if ( halt_on_undef_instruction ) {
            print "***End of simulation\n";
            exit 0;
        }
        print "...continuing simulation...\n";
    }
    if ( log_swi && (0x8 == cpu.ex.pc) ) {
        // SWI - SVC mode
        print "------ Cycle: "; print cpu.cycle; print" ------\n";
        print "SWI ";
        print " R0 = "; printx cpu.byp.R0;
	print " LR = "; printx cpu.byp.R14_SVC;
        print "\n";
    }
    if ( 0xc == cpu.ex.pc ) {
        // ***PREFETCH ABORT*** ABORT mode
        print "------ Cycle: "; print cpu.cycle; print" ------\n";
        print "***PREFETCH ABORT***";
	print " LR = "; printx cpu.byp.R14_ABORT;
	print " CPSR = "; printx cpu.ex.CPSR;
	print " SPSR = "; printx cpu.ex.SPSR_ABORT;
        print "\n";
        if ( halt_on_prefetchabort ) {
            print "***End of simulation\n";
            exit 0;
        }
        print "...continuing simulation...\n";
    }
    if ( 0x10 == cpu.ex.pc ) {
        // ***DATA ABORT*** ABORT mode
        print "------ Cycle: "; print cpu.cycle; print" ------\n";
        print "***DATA ABORT***";
	print " LR = "; printx cpu.byp.R14_ABORT;
	print " CPSR = "; printx cpu.ex.CPSR;
	print " SPSR = "; printx cpu.ex.SPSR_ABORT;
        print "\n";
        if ( halt_on_abort ) {
            print "***End of simulation\n";
            exit 0;
        }
        print "...continuing simulation...\n";
    }
    if ( 0x14 == cpu.ex.pc ) {
        // Unknown ???? mode
        print "------ Cycle: "; print cpu.cycle; print" ------\n";
        print "---unused--- trap at 0x14;";
        print " R14 = "; printx cpu.byp.R14;
        print " CPSR = "; printx cpu.ex.CPSR;
        print "\n";
        print "***End of simulation\n";
        exit 0;
    }
    if ( log_irq && (0x18 == cpu.ex.pc) ) {
	  // IRQ mode
	  print "------ Cycle: "; print cpu.cycle; print" ------\n";
	  print "IRQ:";
	  print " LR = "; printx cpu.byp.R14_IRQ;
	  print " CPSR = "; printx cpu.ex.CPSR;
	  print " SPSR = "; printx cpu.ex.SPSR_IRQ;
	  print "\n";
    }
    if ( 0x1c == cpu.ex.pc ) {
        // FIQ mode
        print "------ Cycle: "; print cpu.cycle; print" ------\n";
        print "FIQ:";
	print " LR = "; printx cpu.byp.R14_FIQ;
	print " CPSR = "; printx cpu.ex.CPSR;
	print " SPSR = "; printx cpu.ex.SPSR_FIQ;
        print "\n";
    }
}

// ----------------------------------------------------------------------
// EOF cpu.pil