sa110_misc.c

Intel XScale PXA255 引导Linux的Redboot 版bootloader源代码！

//==========================================================================
//
//      sa110_misc.c
//
//      HAL misc board support code for StrongARM SA110/SA285
//
//==========================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    gthomas
// Contributors: gthomas
// Date:         1999-02-20
// Purpose:      HAL board support
// Description:  Implementations of HAL board interfaces
//
//####DESCRIPTIONEND####
//
//========================================================================*/

#include <pkgconf/hal.h>
#include <pkgconf/system.h>
#include CYGBLD_HAL_PLATFORM_H
#include CYGHWR_MEMORY_LAYOUT_H

#include <cyg/infra/cyg_type.h>         // base types
#include <cyg/infra/cyg_trac.h>         // tracing macros
#include <cyg/infra/cyg_ass.h>          // assertion macros

#include <cyg/hal/hal_io.h>             // IO macros
#include <cyg/hal/hal_if.h>             // calling interface API
#include <cyg/hal/hal_arch.h>           // Register state info
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_intr.h>           // Interrupt names
#include <cyg/hal/hal_cache.h>
#include <cyg/hal/hal_sa110.h>          // Hardware definitions

#include <cyg/infra/diag.h>             // diag_printf

static void
hal_bsp_mmu_init(int sdram_size);

// Some initialization has already been done before we get here.
//
// Set up the interrupt environment.
// Set up the MMU so that we can use caches.
// Enable caches.
// - All done!

void
do_led(int val, int count)
{
    cyg_uint32 *LED = (cyg_uint32 *)0x40012000;
    int i, j;
    for (i = 0;  i < count;  i++) {
        *LED = val;
        for (j = 0;  j < 0x400000;  j++) ;
        *LED = 3;
        for (j = 0;  j < 0x400000;  j++) ;
    }
}

#if 0
void
show_hex(cyg_uint32 val)
{
    int i;
    cyg_uint32 mask = 0x80000000;
    for (i = 0;  i < 32;  i++) {
        do_led(1, 3);
        if (val & mask) {
            do_led(0, 1);
        } else {
            do_led(2, 1);
        }
        mask >>= 1;
    }
}
#endif

#if 0
#define START_DRAM (cyg_uint32 *)0x00100000
#define END_DRAM   (cyg_uint32 *)0x00800000
#define START_DRAM_QUICK (cyg_uint32 *)0x00100000
#define END_DRAM_QUICK   (cyg_uint32 *)0x00180000

void
dram_test(cyg_uint32 *start_dram, cyg_uint32 *end_dram, cyg_uint32 mask)
{    
    cyg_uint32 *lp, lv;
    cyg_uint8  *bp;

    do_led(3, 5);  do_led(0,1);
    // Check for address
    for (lp = start_dram;  lp < end_dram;  lp += (0x00010000/sizeof(*lp))) {
        *lp = (cyg_uint32)lp;
        if ((mask != 0) && (((cyg_uint32)lp & (mask-1)) == 0)) do_led(2,1);
    }
    for (lp = start_dram;  lp < end_dram;  lp += (0x00010000/sizeof(*lp))) {
        if (*lp != (cyg_uint32)lp) {
            while (true) {
                do_led(0,1); do_led(1,4);
            }
        }
        if ((mask != 0) && (((cyg_uint32)lp & (mask-1)) == 0)) do_led(1,1);
    }
    do_led(3, 5);  do_led(0,2);
    // Check for zeros
    for (lp = start_dram;  lp < end_dram;  lp++) {
        *lp = 0x00000000;
        if ((mask != 0) && (((cyg_uint32)lp & (mask-1)) == 0)) do_led(2,1);
    }
    for (lp = start_dram;  lp < end_dram;  lp++) {
        if (*lp != 0x00000000) {
            while (true) {
                do_led(0,1); do_led(1,1);
            }
        }
        if ((mask != 0) && (((cyg_uint32)lp & (mask-1)) == 0)) do_led(1,1);
    }
    do_led(3, 5);  do_led(0,3);
    // Check for ones
    for (lp = start_dram;  lp < end_dram;  lp++) {
        *lp = 0xFFFFFFFF;
        if ((mask != 0) && (((cyg_uint32)lp & (mask-1)) == 0)) do_led(2,1);
    }
    for (lp = start_dram;  lp < end_dram;  lp++) {
        if (*lp != 0xFFFFFFFF) {
            while (true) {
                do_led(0,1); do_led(1,2);
            }
        }
        if ((mask != 0) && (((cyg_uint32)lp & (mask-1)) == 0)) do_led(1,1);
    }
    do_led(3, 5);  do_led(0,4);
    // Check for address
    for (lp = start_dram;  lp < end_dram;  lp++) {
        *lp = (cyg_uint32)lp;
        if ((mask != 0) && (((cyg_uint32)lp & (mask-1)) == 0)) do_led(2,1);
    }
    for (lp = start_dram;  lp < end_dram;  lp++) {
        if (*lp != (cyg_uint32)lp) {
            while (true) {
                do_led(0,1); do_led(1,3);
            }
        }
        if ((mask != 0) && (((cyg_uint32)lp & (mask-1)) == 0)) do_led(1,1);
    }
    do_led(3, 5);  do_led(0,5);
    // Check for address
    for (lp = start_dram;  lp < end_dram;  lp++) {
        bp = (cyg_uint8 *)lp;
        lv = (cyg_uint32)lp;
        *bp++ = lv;  lv >>= 8;
        *bp++ = lv;  lv >>= 8;
        *bp++ = lv;  lv >>= 8;
        *bp++ = lv;  lv >>= 8;
        if ((mask != 0) && (((cyg_uint32)lp & (mask-1)) == 0)) do_led(2,1);
    }
    for (lp = start_dram;  lp < end_dram;  lp++) {
        if (*lp != (cyg_uint32)lp) {
            while (true) {
                do_led(0,1); do_led(1,3);
            }
        }
        if ((mask != 0) && (((cyg_uint32)lp & (mask-1)) == 0)) do_led(1,1);
    }
}
#endif

void hal_hardware_init(void)
{
#if 0
    dram_test(0x4000, 0x8000, 0x1000);
    do_led(0,3);  do_led(1,10);
    dram_test(START_DRAM_QUICK, END_DRAM_QUICK, 0x1000);
    do_led(0,3);  do_led(1,10);
    dram_test(START_DRAM, END_DRAM, 0x10000);
    do_led(0,3);  do_led(1,10);
#endif

    // Disable all interrupt sources:
    *SA110_IRQCONT_IRQENABLECLEAR = 0xffffffff;
    *SA110_IRQCONT_FIQENABLECLEAR = 0xffffffff; // including FIQ
    // Disable the timers
    *SA110_TIMER1_CONTROL = 0;
    *SA110_TIMER2_CONTROL = 0;
    *SA110_TIMER3_CONTROL = 0;
    *SA110_TIMER4_CONTROL = 0;

    *SA110_TIMER1_CLEAR = 0;            // Clear any pending interrupt
    *SA110_TIMER2_CLEAR = 0;            // (Data: don't care)
    *SA110_TIMER3_CLEAR = 0;
    *SA110_TIMER4_CLEAR = 0;

    // Let the timer run at a default rate (for delays)
    hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD);

    // Set up MMU so that we can use caches
    hal_bsp_mmu_init( 0x01000000 /*hal_dram_size*/ );

    // Enable caches
    HAL_DCACHE_ENABLE();
    HAL_ICACHE_ENABLE();

    // Set up eCos/ROM interfaces
    hal_if_init();
}

// -------------------------------------------------------------------------
// MMU initialization:

static void
hal_bsp_mmu_init(int sdram_size)
{
    unsigned long ttb_base = ((unsigned long)0x4000); // could be external
    unsigned long i;

    /*
     * Set the TTB register
     */
    asm volatile ("mcr  p15,0,%0,c2,c0,0" 
                  :
                  : "r"(ttb_base)
                /*:*/
        );
    /*
     * Set the Domain Access Control Register
     */
    i = ARM_ACCESS_TYPE_MANAGER(0)    | 
        ARM_ACCESS_TYPE_NO_ACCESS(1)  |
        ARM_ACCESS_TYPE_NO_ACCESS(2)  |
        ARM_ACCESS_TYPE_NO_ACCESS(3)  |
        ARM_ACCESS_TYPE_NO_ACCESS(4)  |
        ARM_ACCESS_TYPE_NO_ACCESS(5)  |
        ARM_ACCESS_TYPE_NO_ACCESS(6)  |
        ARM_ACCESS_TYPE_NO_ACCESS(7)  |
        ARM_ACCESS_TYPE_NO_ACCESS(8)  |
        ARM_ACCESS_TYPE_NO_ACCESS(9)  |
        ARM_ACCESS_TYPE_NO_ACCESS(10) |
        ARM_ACCESS_TYPE_NO_ACCESS(11) |
        ARM_ACCESS_TYPE_NO_ACCESS(12) |
        ARM_ACCESS_TYPE_NO_ACCESS(13) |
        ARM_ACCESS_TYPE_NO_ACCESS(14) |
        ARM_ACCESS_TYPE_NO_ACCESS(15);

    asm volatile ("mcr  p15,0,%0,c3,c0,0" 
                  :
                  : "r"(i)
                /*:*/
        );

    /*
     * First clear all TT entries - ie Set them to Faulting
     */
    memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);

    /*
     * We only do direct mapping for the SA110/285 board. That is, all
     * virt_addr == phys_addr.
     */

    /*
     * Actual Base = 0x000(00000)
     * Virtual Base = 0x000(00000)
     * Size = Max SDRAM
     * SDRAM