plf_io.h

Intel XScale PXA255 引导Linux的Redboot 版bootloader源代码！

#ifndef CYGONCE_PLF_IO_H
#define CYGONCE_PLF_IO_H

//=============================================================================
//
//      plf_io.h
//
//      Platform specific IO support
//
//=============================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    hmt, jskov 
// Contributors: hmt, jskov
// Date:         1999-08-09
// Purpose:      Intel SA110 PCI IO support macros
// Description: 
// Usage:        #include <cyg/hal/plf_io.h>
//
// Note:         Based on information in 
//               "21285 Core Logic for SA-110 Microprocessor"
//####DESCRIPTIONEND####
//
//=============================================================================

#include <pkgconf/hal_arm_sa110.h>

#include <cyg/hal/hal_sa110.h>

#include <cyg/hal/hal_io.h>             // IO macros
#include <cyg/hal/hal_platform_ints.h>  // Interrupt vectors

// The PCI resources required by the SA110/285 are hardcoded to the lowest
// addresses in the PCI address space, thus:
// PCI Memory Space
#define SA110_SDRAM_PCI_ADDR   0
#define SA110_SDRAM_PCI_SIZE   (CYGHWR_HAL_ARM_SA110_PCI_MEM_MAP_SIZE)
#define SA110_CSR_MEM_PCI_ADDR (SA110_SDRAM_PCI_SIZE)
#define SA110_CSR_MEM_PCI_SIZE 0x80
// PCI IO Space
#define SA110_CSR_IO_PCI_ADDR  0
#define SA110_CSR_IO_PCI_SIZE  0x80

// Incidentally I now understand why it's necessary to force PCI reset
// (2000-08-07) - with RedBoot in ROM, the RAM app was unconditionally
// reinitializing the PCI bus when it was already initialized, without
// resetting it.  We cannot play the same game here as with
// hal_platform_setup.h - I tried - because otherwise the net cannot
// re-initialize itself; the scan for devices fails.

// Initialize the PCI bus.
#define HAL_PCI_INIT()                                                   \
    CYG_MACRO_START                                                      \
    cyg_uint32 __tmp, __tmp2;                                            \
                                                                         \
    /* Assert PCI_reset                                               */ \
    HAL_READ_UINT32(SA110_CONTROL, __tmp);                               \
    __tmp &= ~SA110_CONTROL_RST_I;                                       \
    HAL_WRITE_UINT32(SA110_CONTROL, __tmp);                              \
                                                                         \
    /* Disable PCI Outbound interrupts                                */ \
    /* (according to 7-14 SA110_OUT_INT_MASK is not accessible        */ \
    /* by SA-100)                                                     */ \
    HAL_WRITE_UINT32(SA110_OUT_INT_STATUS,                               \
                     SA110_OUT_INT_STATUS_DOORBELL_INT                   \
                     |SA110_OUT_INT_STATUS_OUTBOUND_INT);                \
                                                                         \
    /* Disable Doorbells                                              */ \
    HAL_WRITE_UINT32(SA110_DOORBELL_PCI_MASK, 0);                        \
    HAL_WRITE_UINT32(SA110_DOORBELL_SA_MASK, 0);                         \
                                                                         \
    /* Map high PCI address bits to 0                                 */ \
    HAL_WRITE_UINT32(SA110_PCI_ADDR_EXT, 0);                             \
                                                                         \
    /* Interrupt ID to 1                                              */ \
    HAL_WRITE_UINT16(SA110_PCI_CFG_INT_LINE, 0x0100);                    \
                                                                         \
    /* Remove PCI_reset                                               */ \
    HAL_READ_UINT32(SA110_CONTROL, __tmp);                               \
    __tmp |= SA110_CONTROL_RST_I;                                        \
    HAL_WRITE_UINT32(SA110_CONTROL, __tmp);                              \
                                                                         \
    /* Open a window to SDRAM from PCI address space                  */ \
    HAL_WRITE_UINT32(SA110_SDRAM_BASE_ADDRESS_MASK,                      \
           ((CYGHWR_HAL_ARM_SA110_PCI_MEM_MAP_SIZE-1) & 0xfffc0000));  \
    HAL_WRITE_UINT32(SA110_SDRAM_BASE_ADDRESS_OFFSET,                    \
             CYGHWR_HAL_ARM_SA110_PCI_MEM_MAP_BASE);                   \
                                                                         \
    /* Only init PCI if central function is set and */                   \
    /* standalone bit is cleared                    */                   \
    HAL_READ_UINT32(SA110_CONTROL, __tmp);                               \
    HAL_READ_UINT32(SA110_XBUS_XCS2, __tmp2);                            \
    if ((__tmp & SA110_CONTROL_CFN) == SA110_CONTROL_CFN                 \
        && (__tmp2 & SA110_XBUS_XCS2_PCI_DISABLE) == 0) {                \
                                                                         \
        /* Don't respond to any commands                              */ \
        HAL_WRITE_UINT16(SA110_PCI_CFG_COMMAND, 0);                      \
                                                                         \
        /* Set up default addresses for board's resources.            */ \
        HAL_WRITE_UINT32(SA110_PCI_CFG_CSR_MEM_BAR,                      \
                         SA110_CSR_MEM_PCI_ADDR);                         \
        HAL_WRITE_UINT32(SA110_PCI_CFG_CSR_IO_BAR, SA110_CSR_IO_PCI_ADDR);\
        HAL_WRITE_UINT32(SA110_PCI_CFG_SDRAM_BAR, SA110_SDRAM_PCI_ADDR);  \
                                                                         \