📄 hal_platform_setup.h
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/* 4 banks, 1M depth, 16 wide, 2 banks, 12 rows, 8 cols, */ ;\ /* 2 SDRAMS in 1 array, 16MB total, row/col MUX mode 100 */ ;\ /* */ ;\ /* Start by forming the SDRAM mode register's base address in r0 */ ;\ MOV r0,#0x40000000 /* Base for SDRAM array 0 mode reg */ ;\ /* We want to set the SDRAM mode reg to 0x22, but the mapping */ ;\ /* between the physical address pins of the SDRAM and the logical */ ;\ /* address of the SA-110 and the 21285 shift this value to 0x88. */ ;\ /* Set burst length to 4, M2:M0 = 010 */ ;\ /* Set burst type to sequential burst, M3 = 0 */ ;\ /* Set CAS latency to 2, M6:M4 = 010 */ ;\ /* M9 = 0 so bits M2:M0 apply to both reads and writes! */ ;\ /* The contents of r1 is a "don't care" since only the address */ ;\ /* bits get MUXed into the SDRAM mode reg. */ ;\ STR r1, [r0, #0x88] /* Set the SDRAM mode register. */ ;\ ;\/* r0 has the base address */ ;\/* r1 has the full formed reg address */ ;\/* r2 has the reg data */ ;\ ;\ /* Set r0 to the base of the SA-110 Control and Status regs */ ;\ MOV r0, #0x42000000 ;\ /* Form the address of the SDRAM base address mask reg */ ;\ /* Set mask for r/w, i.e. all zeros */ ;\ MOV r2, #0 ;\ STR r2, [r0, #0x100] /* Set the SDRAM base address mask */ ;\ ;\ /* Set the SDRAM timing reg in the 21285. */ ;\ /* Row precharge timing is 2 cycles; 1:0 = 01 */ ;\ /* Last data in to activate is 4 cycles; 3:2 = 10 */ ;\ /* RAS-CAS Delay is 2 cycles; 5:4 = 10 */ ;\ /* CAS latency is 2 cycles; 7:6 = 10 */ ;\ /* Row cycle time is 7 cycles; 10:8 = 100 */ ;\ /* Command drive time is same cycle; bit 11 = 0 */ ;\ /* Parity enable is no parity; bit 12 = 0 */ ;\ /* SA-110 Prime; bit 13 = 0 */ ;\ /* 15:14 = 0 */ ;\ /* Refresh interval 4096/32 so just set to max */ ;\ /* 21:16 = 111111 */ ;\ /* It's no problem to refresh more often than necessary */ ;\ /* all others 0 */ ;\ LDR r2, =0x003F04A9 ;\ STR r2, [r0, #0x10C] /* Set the SDRAM timing reg */ ;\ ;\ /* Set the Array 0 SDRAM address and size reg. We have only one array. */ ;\ /* Reg offset is 0x110 */ ;\ /* Array size is 16MB; 2:0 = 101 */ ;\ /* bit 3 is zero */ ;\ /* Address multiplex is 100; 6:4 = 100 */ ;\ /* bits 19:7 = 0 */ ;\ /* Array base for array 0 is zero; 27:20 = 0 */ ;\ /* bits 31:28 = 0 */ ;\ MOV r2, #0x00000045 /* Data for array 0 of SDRAM */ ;\ STR r2, [r0, #0x110] /* Set the SDRAM address and size reg */ ;\ ;\ /* Disable the other 3 memory arrays by writing all zero */ ;\ MOV r2, #0 ;\ STR r2, [r0, #0x114] /* Disable SDRAM Array 1 */ ;\ STR r2, [r0, #0x118] /* Disable SDRAM Array 2 */ ;\ STR r2, [r0, #0x11C] /* Disable SDRAM Array 3 */ ;\ ;\ /*We need 100us from the setting of the SDRAM mode */ ;\ MOV r3,#0x00005000 /* need more because of I cache */ ;\delay_gt_100us: ;\ SUBS r3,r3,#1 ;\ BNE delay_gt_100us ;\ ;\ LDR r0, =0x40012000 ;\ MOV r3, #0 ;\ STR r3, [r0] /*Turn both LEDs on */ ;\ ;\/* */ ;\/* This ends the SDRAM setup and initialization. */ ;\ ;\ /* Okay, let's exercise memory, write a picket fence */ ;\ /* pattern alternating both halves of memory with */ ;\ /* 0xA5A5A5A5 and 0x5A5A5A5A */ ;\/* Divide memory into 2 halves and ping pong between them in case */ ;\/* the write buffer or floating pins are spoofing us into thinking */ ;\/* that our read/write was successful. */ ;\/* */ ;\/* Test memory from 0 to 0x3fffff (4MB) */ ;\/* r0 is now the memory address */ ;\/* r2 is the data */ ;\/* r3 is XORed data */ ;\/* */ ;\/* Test memory from 0x400000 to 0x7fffff (4MB) */ ;\/* r5 is now the base memory address */ ;\/* r6 is the data */ ;\/* r7 is XORed data */ ;\/* */ ;\/* r4 is a mask of ones, 0xffffffff */ ;\/* r8 is loop test limit */ ;\/* r9 = 0xA5A5A5A5 */ ;\/* r10 = 0x5A5A5A5A */ ;\/* */ ;\/* r1 is free */ ;\ ;\ MOV r0, #0 /* set base for lower half of memory */ ;\ MOV r5, #0x800000 /* set base for upper half of memory */ ;\ MOV r8, #0x800000 /* loop limit */ ;\ MOV r6, #0x40000 /* LED toggle */ ;\ MOV r7, #3 /* LED toggle */ ;\ ;\ /* build the memory picket fence of 0xA5A5A5A5 */ ;\ LDR r9, =0xA5A5A5A5 /* begin pattern */ ;\ LDR r10, =0x5A5A5A5A ;\ ;\memory_loop: ;\ ;\ STR r9, [r0] /* store 0xA5A5A5A5 */ ;\ STR r10, [r5] /* store 0x5A5A5A5A */ ;\ ;\ LDR r2, [r0] ;\ LDR r4, [r5] ;\ ;\ CMP r2, r9 ;\ BNE not_equal ;\ CMP r4, r10 ;\ BNE not_equal ;\ ;\ /* Switch picket fence patterns */ ;\ STR r10, [r0] /* store 0x5A5A5A5A */ ;\ STR r9, [r5] /* store 0xA5A5A5A5 */ ;\ ;\ LDR r2, [r0] ;\ LDR r4, [r5] ;\ ;\ CMP r2, r10 ;\ BNE not_equal ;\ CMP r4, r9 ;\ BNE not_equal ;\ ;\ ADD r0, r0, #4 /* increment lower half address */ ;\ ADD r5, r5, #4 /* increment upper half address */ ;\ cmp r0,r6 ;\ bne 10f ;\ ldr r2,=0x40012000 ;\ str r7,[r2] ;\ add r7,r7,#1 ;\ and r7,r7,#3 ;\ add r6,r6,#0x40000 ;\10: CMP r0, r8 /* did we reach the loop limit? */ ;\ BNE memory_loop ;\ ;\ ;\ /* form the base X-Bus CS2 address in r0 */ ;\good_memory: ;\ LDR r2, =0x40012000 ;\ ;\infinite_loopA: ;\ MOV r3, #1 ;\ STR r3, [r2] /*Turn green LED on */ ;\ ;\ MOV r4,#0x00800000 ;\delayA: ;\ SUBS r4,r4,#1 ;\ BNE delayA ;\ ;\ MOV r3, #3 ;\ STR r3, [r2] /*Turn both LEDs off */ ;\ ;\ MOV r4,#0x00800000 ;\delayB: ;\⌨️ 快捷键说明
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