hal_diag.c

Intel XScale PXA255 引导Linux的Redboot 版bootloader源代码！

/*=============================================================================
//
//      hal_diag.c
//
//      HAL diagnostic output code
//
//=============================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 1998, 1999, 2000 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):   alvin
// Contributors:msalter
// Date:        2002-08-10
// Purpose:     HAL diagnostic output
// Description: Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//===========================================================================*/

#include <pkgconf/hal.h>
#include <pkgconf/system.h>
#include CYGBLD_HAL_PLATFORM_H

#include <cyg/infra/cyg_type.h>         // base types
#include <cyg/infra/cyg_trac.h>         // tracing macros
#include <cyg/infra/cyg_ass.h>          // assertion macros

#include <cyg/hal/hal_arch.h>           // basic machine info
#include <cyg/hal/hal_intr.h>           // interrupt macros
#include <cyg/hal/hal_io.h>             // IO macros
#include <cyg/hal/hal_if.h>             // calling interface API
#include <cyg/hal/hal_misc.h>           // helper functions
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_sitsang.h>        // Hardware definitions
#include <cyg/hal/drv_api.h>            // cyg_drv_interrupt_acknowledge


#define SIO_IER_ERDAI SIO_IER_RAVIE


#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) \
    || defined(CYGPRI_HAL_IMPLEMENTS_IF_SERVICES)

static void cyg_hal_plf_serial_init(void);

/************************************************************/


void writeHexLLed(unsigned short value)
{
	volatile unsigned short *ledReg = (unsigned long *)LLEDR_RW ;

	*ledReg = value ;

	return ;
}

void writeHexRLed(unsigned short value)
{
        volatile unsigned short *ledReg = (unsigned long *)HLEDR_RW ;

        *ledReg = value ;

        return ;
}


void cyg_hal_plf_comms_init(void)
{
    static int initialized = 0;

    if (initialized)
        return;

    initialized = 1;

    cyg_hal_plf_serial_init();
//    cyg_hal_plf_lcd_init();
}
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG || CYGPRI_HAL_IMPLEMENTS_IF_SERVICES

//=============================================================================
// Serial driver
//=============================================================================

//-----------------------------------------------------------------------------
// There are two serial ports.
#define CYG_DEV_SERIAL_BASE_A    0x40100000 // port A
#define CYG_DEV_SERIAL_BASE_B    0x40700000 // port B

//-----------------------------------------------------------------------------
// Default baud rate is 38400
// Based on 14.7456 MHz clock
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
#define CYG_DEV_SERIAL_BAUD_MSB        0x00
#define CYG_DEV_SERIAL_BAUD_LSB        0x60
#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
#define CYG_DEV_SERIAL_BAUD_MSB        0x00
#define CYG_DEV_SERIAL_BAUD_LSB        0x30
#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
#define CYG_DEV_SERIAL_BAUD_MSB        0x00
#define CYG_DEV_SERIAL_BAUD_LSB        0x18
#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
#define CYG_DEV_SERIAL_BAUD_MSB        0x00
#define CYG_DEV_SERIAL_BAUD_LSB        0x10
#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
#define CYG_DEV_SERIAL_BAUD_MSB        0x00
#define CYG_DEV_SERIAL_BAUD_LSB        0x08
#endif

#ifndef CYG_DEV_SERIAL_BAUD_MSB
#error Missing/incorrect serial baud rate defined - CDL error?
#endif

//-----------------------------------------------------------------------------
// Define the serial registers. The Cogent board is equipped with a 16552
// serial chip.
#define CYG_DEV_SERIAL_RBR   0x00  // receiver buffer register, read, dlab = 0
#define CYG_DEV_SERIAL_THR   0x00 // transmitter holding register, write, dlab = 0
#define CYG_DEV_SERIAL_DLL   0x00 // divisor latch (LS), read/write, dlab = 1
#define CYG_DEV_SERIAL_IER   0x04 // interrupt enable register, read/write, dlab = 0
#define CYG_DEV_SERIAL_DLM   0x04 // divisor latch (MS), read/write, dlab = 1
#define CYG_DEV_SERIAL_IIR   0x08 // interrupt identification register, read, dlab = 0
#define CYG_DEV_SERIAL_FCR   0x08 // fifo control register, write, dlab = 0
#define CYG_DEV_SERIAL_LCR   0x0c // line control register, write
#define CYG_DEV_SERIAL_MCR   0x10 // modem control register, write
#define CYG_DEV_SERIAL_LSR   0x14 // line status register, read
#define CYG_DEV_SERIAL_MSR   0x18 // modem status register, read
#define CYG_DEV_SERIAL_SPR   0x1c // scratch pad register
#define CYG_DEV_SERIAL_ISR   0x20 // slow infrared select register (ISR), read/write

// The interrupt enable register bits.
#define SIO_IER_RAVIE   0x01            // enable received data available irq
#define SIO_IER_TIE		  0x02            // enable transmit data request interrupt
#define SIO_IER_RLSE    0x04            // enable receiver line status irq
#define SIO_IER_MIE     0x08            // enable modem status interrupt
#define SIO_IER_RTOIE		0x10            // enable Rx timeout interrupt
#define SIO_IER_NRZE		0x20            // enable NRZ coding
#define SIO_IER_UUE			0x40            // enable the UART unit
#define SIO_IER_DMAE		0x80            // enable DMA requests

// The interrupt identification register bits.
#define SIO_IIR_IP      0x01            // 0 if interrupt pending
#define SIO_IIR_ID_MASK 0xff            // mask for interrupt ID bits
#define ISR_Tx  0x02
#define ISR_Rx  0x04

// The line status register bits.
#define SIO_LSR_DR      0x01            // data ready
#define SIO_LSR_OE      0x02            // overrun error
#define SIO_LSR_PE      0x04            // parity error
#define SIO_LSR_FE      0x08            // framing error
#define SIO_LSR_BI      0x10            // break interrupt
#define SIO_LSR_THRE    0x20            // transmitter holding register empty
#define SIO_LSR_TEMT    0x40            // transmitter holding and Tx shift registers empty
#define SIO_LSR_ERR     0x80            // any error condition (FIFOE)

// The modem status register bits.
#define SIO_MSR_DCTS  0x01              // delta clear to send
#define SIO_MSR_DDSR  0x02              // delta data set ready
#define SIO_MSR_TERI  0x04              // trailing edge ring indicator
#define SIO_MSR_DDCD  0x08              // delta data carrier detect
#define SIO_MSR_CTS   0x10              // clear to send
#define SIO_MSR_DSR   0x20              // data set ready
#define SIO_MSR_RI    0x40              // ring indicator
#define SIO_MSR_DCD   0x80              // data carrier detect

// The modem control register bits
#define SIO_MCR_DTR   0x01                //Data Terminal Ready
#define SIO_MCR_RTS   0x02                //Request to Send
#define SIO_MCR_OUT1  0x04                //Test bit,only used in loop mode
#define SIO_MCR_OUT2  0x08                //OUT2 signal control
#define SIO_MCR_LOOP  0x10                //loop mode 

// The line control register bits.
#define SIO_LCR_WLS0   0x01             // word length select bit 0
#define SIO_LCR_WLS1   0x02             // word length select bit 1
#define SIO_LCR_STB    0x04             // number of stop bits
#define SIO_LCR_PEN    0x08             // parity enable
#define SIO_LCR_EPS    0x10             // even parity select
#define SIO_LCR_SP     0x20             // stick parity
#define SIO_LCR_SB     0x40             // set break
#define SIO_LCR_DLAB   0x80             // divisor latch access bit

// The FIFO control register
#define SIO_FCR_FCR0   0x01             // enable xmit and rcvr fifos
#define SIO_FCR_FCR1   0x02             // clear RCVR FIFO
#define SIO_FCR_FCR2   0x04             // clear XMIT FIFO
#define SIO_FCR_ITL0   0x40             // Interrupt trigger level (ITL) bit 0
#define SIO_FCR_ITL1   0x80             // Interrupt trigger level (ITL) bit 1
#define SIO_FCR_ITL_1BYTE   0x00				// i byte truggers interrupt

#define GPDR0_ADDR 0x40e0000c
#define GPDR1_ADDR 0x40e00010
#define GPDR2_ADDR 0x40e00014
#define GPSR0_ADDR 0x40e00018
#define GPSR1_ADDR 0x40e0001c
#define GPSR2_ADDR 0x40e00020
#define GPCR0_ADDR 0x40e00024
#define GPCR1_ADDR 0x40e00028
#define GPCR2_ADDR 0x40e0002c

#define GAFR0_L_ADDR 0x40e00054
#define GAFR0_U_ADDR 0x40e00058
#define GAFR1_L_ADDR 0x40e0005c
#define GAFR1_U_ADDR 0x40e00060
#define GAFR2_L_ADDR 0x40e00064
#define GAFR2_U_ADDR 0x40e00068

#define CKEN_ADDR 0x41300004


void Delay(int uSec)
{
	int delaytime;
	int starttime;

	delaytime = (int)(uSec*3.6864);
	starttime = *(volatile unsigned long *)OSCR ;
	*(volatile unsigned long *)OSCR = 0;
	while ((*(volatile unsigned long *)OSCR) < delaytime);
}





//-----------------------------------------------------------------------------
typedef struct {
    cyg_uint8* base;
    cyg_int32 msec_timeout;
    int isr_vector;
} channel_data_t;

//-----------------------------------------------------------------------------
static void
init_serial_channel(const channel_data_t* __ch_data)
{
    cyg_uint8* base = __ch_data->base;
    cyg_uint8 lcr, alvin;
    volatile unsigned long * pcr_addr=(unsigned long volatile*)PCR_RW;
    unsigned long value_pcr,value;
    volatile unsigned long * addr;
    
    addr=(volatile unsigned long*) GPDR1_ADDR;
    value = *addr;
    value |= 1<<7 | 1 <<8 | 1<< 9; //GP39-41 AS OUT
    value &= ~( 1<<2 | 1<<3 | 1<<4 | 1<<5 | 1<<6); //GP34-38 AS IN
    *addr = value;

    addr = (volatile unsigned long*) GAFR1_L_ADDR;
    value = *addr;
    value &= ~(0x000ffff0);
    value |= 0x000a9550;
    *addr = value;

    addr = (volatile unsigned long*) CKEN_ADDR;
    value = *addr;
    value |= (0x1<<6);  //enable FFUART unit clock
    *addr = value;

    /* clear sticky status first*/
    alvin = 0x0;
    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, alvin);
    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, alvin);
    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_MCR, alvin);
    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_ISR, alvin);
    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_IER, alvin);



    // 8-1-no parity.
    lcr = SIO_LCR_WLS0 | SIO_LCR_WLS1;
    lcr |= SIO_LCR_DLAB;
    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);

		//	Setup divisor
    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);

		//	DLAB = 0 to allow access to FIFOs
    lcr &= ~SIO_LCR_DLAB;
    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_LCR, lcr);

    //close loopback mode
    HAL_READ_UINT8(base+CYG_DEV_SERIAL_MCR,alvin);
    alvin &= ~(SIO_MCR_LOOP);
    //enable DTR, RTS
    alvin |= SIO_MCR_DTR | SIO_MCR_RTS| SIO_MCR_OUT2; 
    HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_MCR,alvin);
    //read msr once to clear delta bits, (bits 3:0)
    HAL_READ_UINT8(base+CYG_DEV_SERIAL_MSR,alvin);

	    
		//  Enable & clear FIFOs
		//  set Interrupt Trigger Level to be 1 byte
		HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_FCR, (SIO_FCR_FCR0 | SIO_FCR_FCR1 | SIO_FCR_FCR2));  // Enable & clear FIFO

		//	Configure NRZ, disable DMA requests and enable UART
		HAL_WRITE_UINT8(base+CYG_DEV_SERIAL_IER, SIO_IER_UUE);

		value_pcr=*pcr_addr;
		value_pcr |= PCR_RS232_ON | PCR_PER_ON;   //RS232 on 
		*pcr_addr = value_pcr;
		
}

static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
    cyg_uint8 lsr;

    HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
    if ((lsr & SIO_LSR_DR) == 0){
        return false;
    }
   
    HAL_READ_UINT8(base+CYG_DEV_SERIAL_RBR, *ch);
    return true;
}


cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
    cyg_uint8 ch;
    CYGARC_HAL_SAVE_GP();

    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));

    CYGARC_HAL_RESTORE_GP();
    return ch;
}

void
cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 c)
{
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
    cyg_uint8 lsr;
    CYGARC_HAL_SAVE_GP();

    do {
        HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
    } while ((lsr & SIO_LSR_THRE) == 0);

		HAL_WRITE_UINT8(FFTHR, c);

    // Hang around until the character has been safely sent.
   do {
        HAL_READ_UINT8(base+CYG_DEV_SERIAL_LSR, lsr);
    } while ((lsr & SIO_LSR_THRE) == 0);