cotulla_def.h

Intel XScale PXA255 引导Linux的Redboot 版bootloader源代码！

/**********************************************                  
 * XScale1(R) register location  definitions  *          
 **********************************************/                 
// Application Engineering   
// Purpose: Describes all registers mapped in the XScale Microarchitecture Processor. 
// (Note: Does not include Co-processer registers)
//
// File: cotulla_def.h                

//     Memory Controller 0x48000000            
#define MDCNFG     (volatile unsigned long *)( 0x48000000 )          // SDRAM configuration register 0
#define MDREFR     (volatile unsigned long *)( 0x48000004 )          // SDRAM refresh control register
#define MSC0       (volatile unsigned long *)( 0x48000008 )          // Static memory control register 0
#define MSC1       (volatile unsigned long *)( 0x4800000C )          // Static memory control register 1
#define MSC2       (volatile unsigned long *)( 0x48000010 )          // Static memory control register 2
#define MECR       (volatile unsigned long *)( 0x48000014 )          // Expansion memory (PCMCIA / Compact Flash) bus configuration register
#define SXLCR      (volatile unsigned long *)( 0x48000018 )          // LCR value to be written to SDRAM-Timing Synchronous Flash
#define SXCNFG     (volatile unsigned long *)( 0x4800001C )          // Synchronous static memory control register
#define FLYCNFG    (volatile unsigned long *)( 0x48000020 )          // Fly by DMA DVAL assert and deassert times
#define SXMRS      (volatile unsigned long *)( 0x48000024 )          // MRS value to be written to Synchronous Flash or SMROM
#define MCMEM0     (volatile unsigned long *)( 0x48000028 )          // Card interface Common Memory Space Socket 0 Timing Configuration
#define MCMEM1     (volatile unsigned long *)( 0x4800002C )          // Card interface Common Memory Space Socket 1 Timing Configuration
#define MCATT0     (volatile unsigned long *)( 0x48000030 )          // Card interface Attribute Space Socket 0 Timing Configuration
#define MCATT1     (volatile unsigned long *)( 0x48000034 )          // Card interface Attribute Space Socket 1 Timing Configuration
#define MCIO0      (volatile unsigned long *)( 0x48000038 )          // Card interface I/O Space Socket 0 Timing Configuration
#define MCIO1      (volatile unsigned long *)( 0x4800003C )          // Card interface I/O Space Socket 1 Timing Configuration
#define MDMRS      (volatile unsigned long *)( 0x48000040 )          // MRS value to be written to SDRAM
#define BOOTDEF    (volatile unsigned long *)( 0x48000044 )          // Read-Only Boot-time register. Contains BOOT_SEL and PKG_SEL values.
//     LCD Controller 0x44000000  
#define LCCR0      (volatile unsigned long *)( 0x44000000 )          // LCD controller control register 0
#define LCCR1      (volatile unsigned long *)( 0x44000004 )          // LCD controller control register 1
#define LCCR2      (volatile unsigned long *)( 0x44000008 )          // LCD controller control register 2
#define LCCR3      (volatile unsigned long *)( 0x4400000C )          // LCD controller control register 3
#define FDADR0     (volatile unsigned long *)( 0x44000200 )          // DMA channel 0 frame descriptor address register
#define FSADR0     (volatile unsigned long *)( 0x44000204 )          // DMA channel 0 frame source address register
#define FIDR0      (volatile unsigned long *)( 0x44000208 )          // DMA channel 0 frame ID register
#define LDCMD0     (volatile unsigned long *)( 0x4400020C )          // DMA channel 0 command register
#define FDADR1     (volatile unsigned long *)( 0x44000210 )          // DMA channel 1 frame descriptor address register
#define FSADR1     (volatile unsigned long *)( 0x44000214 )          // DMA channel 1 frame source address register
#define FIDR1      (volatile unsigned long *)( 0x44000218 )          // DMA channel 1 frame ID register
#define LDCMD1     (volatile unsigned long *)( 0x4400021C )          // DMA channel 1 command register
#define FBR0       (volatile unsigned long *)( 0x44000020 )          // DMA channel 0 frame branch register
#define FBR1       (volatile unsigned long *)( 0x44000024 )          // DMA channel 1 frame branch register
#define LCSR       (volatile unsigned long *)( 0x44000038 )          // LCD controller status register
#define LIIDR      (volatile unsigned long *)( 0x4400003C )          // LCD controller interrupt ID register
#define TRGBR      (volatile unsigned long *)( 0x44000040 )          // TMED RGB Seed Register
#define TCR        (volatile unsigned long *)( 0x44000044 )          // TMED Control Register
//     DMA Controller 0x40000000  
#define DCSR0      (volatile unsigned long *)( 0x40000000 )          // DMA Control / Status Register for Channel 0
#define DCSR1      (volatile unsigned long *)( 0x40000004 )          // DMA Control / Status Register for Channel 1
#define DCSR2      (volatile unsigned long *)( 0x40000008 )          // DMA Control / Status Register for Channel 2
#define DCSR3      (volatile unsigned long *)( 0x4000000c )          // DMA Control / Status Register for Channel 3
#define DCSR4      (volatile unsigned long *)( 0x40000010 )          // DMA Control / Status Register for Channel 4
#define DCSR5      (volatile unsigned long *)( 0x40000014 )          // DMA Control / Status Register for Channel 5
#define DCSR6      (volatile unsigned long *)( 0x40000018 )          // DMA Control / Status Register for Channel 6
#define DCSR7      (volatile unsigned long *)( 0x4000001c )          // DMA Control / Status Register for Channel 7
#define DCSR8      (volatile unsigned long *)( 0x40000020 )          // DMA Control / Status Register for Channel 8
#define DCSR9      (volatile unsigned long *)( 0x40000024 )          // DMA Control / Status Register for Channel 9
#define DCSR10     (volatile unsigned long *)( 0x40000028 )          // DMA Control / Status Register for Channel 10
#define DCSR11     (volatile unsigned long *)( 0x4000002c )          // DMA Control / Status Register for Channel 11
#define DCSR12     (volatile unsigned long *)( 0x40000030 )          // DMA Control / Status Register for Channel 12
#define DCSR13     (volatile unsigned long *)( 0x40000034 )          // DMA Control / Status Register for Channel 13
#define DCSR14     (volatile unsigned long *)( 0x40000038 )          // DMA Control / Status Register for Channel 14
#define DCSR15     (volatile unsigned long *)( 0x4000003c )          // DMA Control / Status Register for Channel 15
#define DINT       (volatile unsigned long *)( 0x400000f0 )          // DMA Interrupt Register
#define DRCMR0     (volatile unsigned long *)( 0x40000100 )          // Request to Channel Map Register for DREQ 0 (companion chip request 0)
#define DRCMR1     (volatile unsigned long *)( 0x40000104 )          // Request to Channel Map Register for DREQ 1 (companion chip request 1)
#define DRCMR2     (volatile unsigned long *)( 0x40000108 )          // Request to Channel Map Register for I2S receive Request
#define DRCMR3     (volatile unsigned long *)( 0x4000010c )          // Request to Channel Map Register for I2S transmit Request
#define DRCMR4     (volatile unsigned long *)( 0x40000110 )          // Request to Channel Map Register for BTUART receive Request
#define DRCMR5     (volatile unsigned long *)( 0x40000114 )          // Request to Channel Map Register for BTUART transmit Request.
#define DRCMR6     (volatile unsigned long *)( 0x40000118 )          // Request to Channel Map Register for FFUART receive Request
#define DRCMR7     (volatile unsigned long *)( 0x4000011c )          // Request to Channel Map Register for FFUART transmit Request
#define DRCMR8     (volatile unsigned long *)( 0x40000120 )          // Request to Channel Map Register for AC97 microphone Request
#define DRCMR9     (volatile unsigned long *)( 0x40000124 )          // Request to Channel Map Register for AC97 modem receive Request
#define DRCMR10    (volatile unsigned long *)( 0x40000128 )          // Request to Channel Map Register for AC97 modem transmit Request
#define DRCMR11    (volatile unsigned long *)( 0x4000012c )          // Request to Channel Map Register for AC97 audio receive Request
#define DRCMR12    (volatile unsigned long *)( 0x40000130 )          // Request to Channel Map Register for AC97 audio transmit Request
#define DRCMR13    (volatile unsigned long *)( 0x40000134 )          // Request to Channel Map Register for SSP receive Request
#define DRCMR14    (volatile unsigned long *)( 0x40000138 )          // Request to Channel Map Register for SSP transmit Request
#define DRCMR15    (volatile unsigned long *)( 0x4000013c )          // Reserved
#define DRCMR16    (volatile unsigned long *)( 0x40000140 )          // Reserved
#define DRCMR17    (volatile unsigned long *)( 0x40000144 )          // Request to Channel Map Register for ICP receive Request
#define DRCMR18    (volatile unsigned long *)( 0x40000148 )          // Request to Channel Map Register for ICP transmit Request
#define DRCMR19    (volatile unsigned long *)( 0x4000014c )          // Request to Channel Map Register for STUART receive Request
#define DRCMR20    (volatile unsigned long *)( 0x40000150 )          // Request to Channel Map Register for STUART transmit Request
#define DRCMR21    (volatile unsigned long *)( 0x40000154 )          // Request to Channel Map Register for MMC receive Request
#define DRCMR22    (volatile unsigned long *)( 0x40000158 )          // Request to Channel Map Register for MMC transmit Request
#define DRCMR23    (volatile unsigned long *)( 0x4000015c )          // RESERVED
#define DRCMR24    (volatile unsigned long *)( 0x40000160 )          // RESERVED
#define DRCMR25    (volatile unsigned long *)( 0x40000164 )          // Request to Channel Map Register for USB endpoint 1 Request
#define DRCMR26    (volatile unsigned long *)( 0x40000168 )          // Request to Channel Map Register for USB endpoint 2 Request
#define DRCMR27    (volatile unsigned long *)( 0x4000016C )          // Request to Channel Map Register for USB endpoint 3 Request
#define DRCMR28    (volatile unsigned long *)( 0x40000170 )          // Request to Channel Map Register for USB endpoint 4 Request
#define DRCMR29    (volatile unsigned long *)( 0x40000174 )          // RESERVED
#define DRCMR30    (volatile unsigned long *)( 0x40000178 )          // Request to Channel Map Register for USB endpoint 6 Request
#define DRCMR31    (volatile unsigned long *)( 0x4000017C )          // Request to Channel Map Register for USB endpoint 7 Request
#define DRCMR32    (volatile unsigned long *)( 0x40000180 )          // Request to Channel Map Register for USB endpoint 8 Request
#define DRCMR33    (volatile unsigned long *)( 0x40000184 )          // Request to Channel Map Register for USB endpoint 9 Request
#define DRCMR34    (volatile unsigned long *)( 0x40000188 )          // RESERVED
#define DRCMR35    (volatile unsigned long *)( 0x4000018C )          // Request to Channel Map Register for USB endpoint 11 Request
#define DRCMR36    (volatile unsigned long *)( 0x40000190 )          // Request to Channel Map Register for USB endpoint 12 Request
#define DRCMR37    (volatile unsigned long *)( 0x40000194 )          // Request to Channel Map Register for USB endpoint 13 Request
#define DRCMR38    (volatile unsigned long *)( 0x40000198 )          // Request to Channel Map Register for USB endpoint 14 Request
#define DRCMR39    (volatile unsigned long *)( 0x4000019C )          // RESERVED
#define DDADR0     (volatile unsigned long *)( 0x40000200 )          // DMA Descriptor Address Register channel 0
#define DSADR0     (volatile unsigned long *)( 0x40000204 )          // DMA Source Address Register channel 0
#define DTADR0     (volatile unsigned long *)( 0x40000208 )          // DMA Target Address Register channel 0
#define DCMD0      (volatile unsigned long *)( 0x4000020C )          // DMA Command Address Register channel 0
#define DDADR1     (volatile unsigned long *)( 0x40000210 )          // DMA Descriptor Address Register channel 1
#define DSADR1     (volatile unsigned long *)( 0x40000214 )          // DMA Source Address Register channel 1
#define DTADR1     (volatile unsigned long *)( 0x40000218 )          // DMA Target Address Register channel 1
#define DCMD1      (volatile unsigned long *)( 0x4000021C )          // DMA Command Address Register channel 1
#define DDADR2     (volatile unsigned long *)( 0x40000220 )          // DMA Descriptor Address Register channel 2
#define DSADR2     (volatile unsigned long *)( 0x40000224 )          // DMA Source Address Register channel 2
#define DTADR2     (volatile unsigned long *)( 0x40000228 )          // DMA Target Address Register channel 2