hal_sitsang.h

Intel XScale PXA255 引导Linux的Redboot 版bootloader源代码！

#ifndef CYGONCE_HAL_SITSANG_H
#define CYGONCE_HAL_SITSANG_H


/*=============================================================================
//
//      hal_sitsang.h
//
//      HAL Description of Sitsang control registers
//      and ARM memory control in general.
//
//=============================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License"); you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    alvin
// Contributors: alvin
// Date:         2002-08-28
// Purpose:      Intel SITSANG hardware description
// Description:
// Usage:        #include <cyg/hal/hal_sitsang.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/

/*******************/
/* Sitsang Devices */
/*******************/


#define BOOT_ROM       0x00000000    /* Boot ROM (Flash) */
#define APP_FLASH      0x00100000    /* Application Flash */
#define SITSANG_REGS   0x08000000    /* Sitsang Registers */
#define SDRAM_B0       0xA0000000    /* 64 MByte of SDRAM Bank 0 */
#define ETHER_CONTR    0x04000000    /* Ethernet Controller IO Space */

#define BOOTFLASHSIZE  0x00100000      /* BOOT FLASH - 1 Mbytes */

#ifdef SITSANG_FLASH_SINGLE_BANK
  #define APPFLASHSIZE   0x01f00000
#else
  #define APPFLASHSIZE   0x03f00000
#endif

#define SDRAMBANK0SIZE 0x4000000     /* SDRAM bank 0 - 64 Mbytes */


/*********************************/
/* Sitsang Board Level Register  */
/*********************************/
#define PCR_RW    (0x08000000)   //Power control register 

#define BCR_RW    (0x08000004)   //Board control register

#define BSR_RD    (0x08000008)   //Board status register

#define BIPR_RW   (0x0800000C)   //Board interrupt pending register

#define BIMR_RW   (0x08000010)   //Board interrupt mask register

#define AXHR_RD   (0x08000014)   //Accelerometer x direction low level counter

#define AXLR_RD   (0x08000018)   //Accelerometer y direction high level counter

#define AYHR_RD   (0x0800001C)   //Accelerometer y direction low level counter

#define JSSR_RD   (0x08000020)   //Joystick switch status register

#define LLEDR_RW  (0x08000024)   //Low 16-bits LED matrix register

#define HLEDR_RW  (0x08000028)   //High 16-bits LED matrix Register

#define EXBCR_RW  (0x0800002C)   //Expansion card board control Register

#define EXBSR_RD  (0x08000030)   //Expansion card board status register

#define EXBIPR_RW (0x08000034)   //Expansion card interrupt pending register

#define EXBIMR_RW (0x08000038)   //Expansion card interrupt mask register

//LED matrix bit definition
#define DISPLAY_0       0x0
#define DISPLAY_1       0x10
#define DISPLAY_2       0x100
#define DISPLAY_3       0x1000
#define DISPLAY_4       0x10000
#define DISPLAY_5       0x100000
#define DISPLAY_6       0x1000000
#define DISPLAY_7       0x10000000
#define DISPLAY_8       0x1
#define DISPLAY_9       0x11
#define DISPLAY_A       0x111
#define DISPLAY_B       0x1111
#define DISPLAY_C       0x11111
#define DISPLAY_D       0x111111
#define DISPLAY_E       0x1111111
#define DISPLAY_F       0x11111111


// Sitsang Board Level Register Bit field defintion
#define		PCR_CF_ON		(0x1)
#define		PCR_USB_HOST_ON		(0x1<<1)
#define		PCR_RS232_ON		(0x1<<2)
#define		PCR_BTUART_ON		(0x1<<3)
#define		PCR_SD_ON		(0x1<<4)
#define		PCR_ACC_ON		(0x1<<5)
#define		PCR_LCD_ON		(0x1<<6)
#define		PCR_LIGHT_ON		(0x1<<7)
#define		PCR_IRDA_ON		(0x1<<8)
#define		PCR_AUDIO_ON		(0x1<<9)
#define		PCR_LAN_ON		(0x1<<10)
#define		PCR_VCC_CHANGE_ON	(0x1<<11)
#define		PCR_PER_ON		(0x1<<14)
#define		PCR_SOFT_PWR_OFF	(0x1<<15)

#define         BCR_FLASH_BO_WP         (0x1)
#define         BCR_FLASH_B1_WP         (0x1<<1)
#define         BCR_BUS_OPEN            (0x1<<2)
#define         BCR_CF_RESET            (0x1<<3)
#define         BCR_CF_CSEL             (0x1<<4)
#define         BCR_USB_NDP             (0x1<<5)
#define         BCR_USB_HC_RESET        (0x1<<6)
#define         BCR_USB_HC_WAKE         (0x1<<7)
#define         BCR_USB_DC_PULL_UP      (0x1<<8)
#define         BCR_IR_MODE_L           (0x1<<9)
#define		BCR_IR_MODE_H		(0x1<<10)
#define		BCR_IR_FSEL		(0x1<<11)
#define         BCR_LAN_RESET           (0x1<<12)
#define         BCR_LAN_NEN16           (0x1<<13)
#define         BCR_EXBD_USE_ECLK       (0x1<<14)
#define         BCR_SYS_NRESET          (0x1<<15)

#define         BSR_CF_VS1              (0x1)
#define         BSR_SD_WP               (0x1<<1)
#define         BSR_BOOTFROM_0          (0x1<<2)
#define         BSR_USB_HC_SUSPEND      (0x1<<3)
#define         BSR_TS_PEN_DOWN         (0x1<<4)
#define         BSR_EXBD_INSERT         (0x1<<5)
#define         BSR_USB_DC_INSERT       (0x1<<6)
#define         BSR_CF_nIRQ_RDY_STATUS  (0x1<<7)
#define         BSR_SMSC_nINT_STATUS    (0x1<<8)
#define         BSR_USB_HC1_OC          (0x1<<9)
#define         BSR_USB_HC2_OC          (0x1<<10)
#define         BSR_BATT_CHARGING       (0x1<<11)
#define         BSR_BTUART_INSERT       (0x1<<12)
#define         BSR_RS232_INSERT        (0x1<<13)
#define		BSR_CF_CARD_INSERT	(0x1<<14)
#define		BSR_SD_INSERT		(0x1<<15)


/**********************************************************************
 * cotulla defintion begin
 * Dont need to change anything for XScale PXA250
 *********************************************************************/

//     Memory Controller 0x48000000            
#define MDCNFG     ( 0x48000000 )          // SDRAM configuration register 0
#define MDREFR     ( 0x48000004 )          // SDRAM refresh control register
#define MSC0       ( 0x48000008 )          // Static memory control register 0
#define MSC1       ( 0x4800000C )          // Static memory control register 1
#define MSC2       ( 0x48000010 )          // Static memory control register 2
#define MECR      ( 0x48000014 )          // Expansion memory (PCMCIA / Compact Flash) bus configuration register
#define SXLCR      ( 0x48000018 )          // LCR value to be written to SDRAM-Timing Synchronous Flash
#define SXCNFG     ( 0x4800001C )          // Synchronous static memory control register
#define FLYCNFG    ( 0x48000020 )          // Fly by DMA DVAL assert and deassert times
#define SXMRS      ( 0x48000024 )          // MRS value to be written to Synchronous Flash or SMROM
#define MCMEM0     ( 0x48000028 )          // Card interface Common Memory Space Socket 0 Timing Configuration
#define MCMEM1     ( 0x4800002C )          // Card interface Common Memory Space Socket 1 Timing Configuration
#define MCATT0     ( 0x48000030 )          // Card interface Attribute Space Socket 0 Timing Configuration
#define MCATT1     ( 0x48000034 )          // Card interface Attribute Space Socket 1 Timing Configuration
#define MCIO0      ( 0x48000038 )          // Card interface I/O Space Socket 0 Timing Configuration
#define MCIO1      ( 0x4800003C )          // Card interface I/O Space Socket 1 Timing Configuration
#define MDMRS      ( 0x48000040 )          // MRS value to be written to SDRAM
#define BOOTDEF    ( 0x48000044 )          // Read-Only Boot-time register. Contains BOOT_SEL and PKG_SEL values.
//     LCD Controller 0x44000000  
#define LCCR0      ( 0x44000000 )          // LCD controller control register 0
#define LCCR1      ( 0x44000004 )          // LCD controller control register 1