hal_platform_setup.h

Intel XScale PXA255 引导Linux的Redboot 版bootloader源代码！

@****************************************************************************
@  Step 10
@
        
        @ write mdmrs
        @
        ldr     r2,  =MDMRS_VAL
        str     r2,  [r1, #MDMRS_OFFSET]
        
        
@****************************************************************************
@  Step 11: Final Step
@
    
        @!!! errata: don't enable auto power-down for A0
        @get current value of mdrefr
        @
        @ldr     r3,  [r1, #MDREFR_OFFSET]
        
        @enable auto-power down 
        @
        @orr     r3,  r3,  #MDREFR_APD
        
        @write back mdrefr
        @
        @str     r3,  [r1, #MDREFR_OFFSET]
        
#if 1
        mov     r0, #0x10000
1:  
	subs    r0,r0,#1
        bne     1b
#endif

@INITINTC        
        @********************************************************************
        @ Disable (mask) all interrupts at the interrupt controller
        @

        @ clear the interrupt level register (use IRQ, not FIQ)
        @
        mov     r1, #0
        ldr     r2,  =ICLR_BASE_PHYSICAL
        str     r1,  [r2]
        
        @ mask all interrupts at the controller
        @       
        ldr     r2,  =ICMR_BASE_PHYSICAL

        str     r1,  [r2]


@INITCLKS        
        @ ********************************************************************        
        @ Disable the peripheral clocks, and set the core clock
        @ frequency (hard-coding at 398.12MHz for now).
        @

		@ Turn Off ALL on-chip peripheral clocks for re-configuration
		@ *Note: See label 'ENABLECLKS' for the re-enabling
		@
        ldr     r1,  =CKEN_BASE_PHYSICAL
        mov     r2,  #0
        str     r2,  [r1]
        
	@set to default frequency if pll bit=0
	@we set the default frequency according to the value of HexSwitch
	@the numbers stand for: Turbo Mode Freq/Run Mode Freq/PxBus Freq/SDram Freq
	@0~3: 300/200/100/100 ;   
	@4~7: 400/200/100/100
	@8-11: 200/200/100/100
	@12-15: 400/400/200/100
	
	getHexSwitch  r0, r3
	cmp	r0, #0x0
	ldreq	r2,  =CORE_CLK_300MHZ
	cmp	r0, #0x01
	ldreq	r2,  =CORE_CLK_300MHZ
	cmp	r0, #0x02
	ldreq   r2,  =CORE_CLK_300MHZ
	cmp	r0, #0x03
	ldreq   r2,  =CORE_CLK_300MHZ
	
	cmp	r0, #0x04
	ldreq   r2,  =CORE_CLK_400MHZ
	cmp     r0, #0x05
    ldreq   r2,  =CORE_CLK_400MHZ
	cmp     r0, #0x06
    ldreq   r2,  =CORE_CLK_400MHZ
	cmp     r0, #0x07
	ldreq   r2,  =CORE_CLK_400MHZ

	cmp 	r0, #0x08
	ldreq	r2, =CORE_CLK_200MHZ
	cmp		r0, #0x09
	ldreq	r2, =CORE_CLK_200MHZ
	cmp		r0, #0x0a
	ldreq	r2, =CORE_CLK_200MHZ
	cmp		r0, #0x0b
	ldreq	r2, =CORE_CLK_200MHZ
	
	cmp		r0, #0x0b
	ldrhi	r2, =CORE_CLK_400MHZ_2
	

        @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
           
        @... and write the core clock config register
        @
        ldr     r1,  =CCCR_BASE_PHYSICAL
        str     r2,  [r1]

        @ enable the 32Khz oscillator for RTC and PowerManager
        @
        ldr     r1,  =OSCC_BASE_PHYSICAL        
        mov     r2,  #OSCC_OON  
        str     r2,  [r1]

	
        @ NOTE:  spin here until OSCC.OOK get set,
        @        meaning the PLL has settled.
        @ 
60:        
        ldr     r2, [r1]
        ands    r2, r2, #1
        beq     60b

@OSCC_OON_DONE        
@add by alvin, finish INIT_CLOCK
	
        @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
        @ initiate the frequency change sequence
        @
        @
        
	getHexSwitch	r0, r2
	cmp		r0, #0x8
	bhi		changeover

        mov r1, #0x2             @ frequency change bit
        mcr p14, 0, r1, c6, c0, 0       @ write CCLKCFG
	
	mov r1, #0x1
	mcr p14, 0, r1, c6, c0, 0

	mov r1, #0x2
	mcr p14, 0, r1, c6, c0, 0

	mov r1, #0x1
	mcr p14, 0, r1, c6, c0, 0
	b	changeturbo
	
changeover:
	mov r1, #0x2
	mcr p14, 0, r1, c6, c0, 0
	
changeturbo:
        @                                                                     @           
        @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

	
	@#ifdef  A0_COTULLA    
    @****************************************************************************
    @ !!! Take care of A0 Errata Sighting #4 -- 
    @ after a frequency change, the memory controller must be restarted
    @

        @ get memory controller base address
        ldr     r1,  =MEMC_BASE_PHYSICAL

        @ get the current state of MDREFR
        @
        ldr     r2,  [r1, #MDREFR_OFFSET]

        @ clear E0PIN, E1PIN
        @
        bic     r3,  r2,  #(MDREFR_E0PIN | MDREFR_E1PIN)

        @ write MDREFR with E0PIN, E1PIN cleared (disable sdclk[0,1])
        @
        str     r3,  [r1, #MDREFR_OFFSET]

        @ then write MDREFR with E0PIN, E1PIN set (enable sdclk[0,1])
        @
        str     r2,  [r1, #MDREFR_OFFSET]

        @ get the current state of MDCNFG
        @
        ldr     r3,  [r1, #MDCNFG_OFFSET]

        @ disable all SDRAM banks
        @
        bic     r3,  r3,  #(MDCNFG_DE0 | MDCNFG_DE1)
        bic     r3,  r3,  #(MDCNFG_DE2 |  MDCNFG_DE3)
     
        @ write back MDCNFG   
        @
        ldr     r3,  [r1, #MDCNFG_OFFSET]

	    @ Access memory not yet enabled for CBR refresh cycles (8)
        @ - CBR is generated for *all* banks
	    ldr     r2, =SDRAM_BASE_PHYSICAL
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]

        @ fetch current mdcnfg value
        @
        ldr     r3,  [r1, #MDCNFG_OFFSET]

        @ enable sdram bank 0 if installed
        @
        orr     r3,  r3,  #MDCNFG_DE0

        @ write back mdcnfg, enabling the sdram bank(s)
        @
        str     r3,  [r1, #MDCNFG_OFFSET]

        @ write mdmrs
        @
        ldr     r2,  =MDMRS_VAL
        str     r2,  [r1, #MDMRS_OFFSET]

        
        
        @ errata: don't enable auto power-down
        @ get current value of mdrefr
        @ldr     r3,  [r1, #MDREFR_OFFSET]
        @ enable auto-power down 
        @orr     r3,  r3,  #MDREFR_APD
        @write back mdrefr
        @str     r3,  [r1, #MDREFR_OFFSET]
    
	@#endif A0_Cotulla

	//we can add leds to help debug here, alvin

@ ^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%
@ ^%^%^%^%^%^%^%^%^%   above could be replaced by prememLLI ^%^%^%^%^%^%^%^%^%
@ ^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%


#if 1  
	// scrub/init SDRAM if enabled/present
	ldr	r11, =0xa0000000 //RAM_BASE	// base address of SDRAM
	ldr	r12, =0x04000000		// size of memory to scrub
	mov	r8,r12		// save DRAM size
	mov	r0, #0		// scrub with 0x0000:0000
	mov	r1, #0
	mov	r2, #0				
	mov	r3, #0
	mov	r4, #0					
	mov	r5, #0
	mov	r6, #0					
	mov	r7, #0
10: // fastScrubLoop
	subs	r12, r12, #32	// 32 bytes/line
	stmia	r11!, {r0-r7}
	beq	15f
	b	10b
15:
	// Save SDRAM size
	ldr     r1, =hal_dram_size  // [see hal_intr.h] 
	str	r8, [r1]
#endif	

	/* keep the enable access instructions */
	// Enable access to all coprocessor registers
	ldr	r0, =0x2001			// enable access to all coprocessors
	mcr	p15, 0, r0, c15, c1, 0

	mcr	p15, 0, r0, c7, c10, 4		// drain the write & fill buffers
	CPWAIT r0	
	
	mcr	p15, 0, r0, c7, c7, 0		// flush Icache, Dcache and BTB
	CPWAIT r0	
	
	mcr	p15, 0, r0, c8, c7, 0		// flush instuction and data TLBs
	CPWAIT r0	
	
	// Enable the Icache
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #MMU_Control_I
	mcr	p15, 0, r0, c1, c0, 0
	CPWAIT  r0
	
	// Set the TTB register
	ldr	r0, =mmu_table
	mcr	p15, 0, r0, c2, c0, 0
	// Enable permission checks in all domains
	ldr	r0, =0x55555555
	mcr	p15, 0, r0, c3, c0, 0

	
	// Enable the MMU
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #MMU_Control_M
	orr	r0, r0, #MMU_Control_R
	mcr	p15, 0, r0, c1, c0, 0
	CPWAIT  r0
	
	mcr	p15, 0, r0, c7, c10, 4		// drain the write & fill buffers
	CPWAIT r0	
	
	// Enable the Dcache
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #MMU_Control_C
	mcr	p15, 0, r0, c1, c0, 0
	CPWAIT  r0

	// Enable the BTB
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #MMU_Control_BTB
	mcr	p15, 0, r0, c1, c0, 0
	CPWAIT  r0

	//we can add leds here to help debug, alvin
	
	CPWAIT r0
	// clean/drain/flush the main Dcache
	mov	r1, #DCACHE_FLUSH_AREA           // use a CACHEABLE area of
	                                         // the memory map above SDRAM
	mov	r0, #1024			 // number of lines in the Dcache
20:
	mcr	p15, 0, r1, c7, c2, 5		 // allocate a Dcache line
	/* increment the address to the next cache line */
	add	r1, r1, #32	
	// decrement the loop count
	subs	r0, r0, #1			 // decrement the loop count
	bne	20b

	//we can add leds to help debug here


	// clean/drain/flush the mini Dcache
	ldr	r2, =(DCACHE_FLUSH_AREA+DCACHE_SIZE) // use a CACHEABLE area of
  	                                       // the memory map above SDRAM
	mov	r0, #64			        // number of lines in the mini Dcache
21:
	mcr	p15, 0, r2, c7, c2, 5		// allocate a Dcache line
	add	r2, r2, #32			// increment the address to
  	                                        // the next cache line
	subs	r0, r0, #1			// decrement the loop count
	bne	21b

	mcr	p15, 0, r0, c7, c6, 0		// flush Dcache
	CPWAIT r0

	mcr	p15, 0, r0, c7, c10, 4		// drain the write & fill buffers
	CPWAIT r0	

	//we can add leds to help debug here
	

#if 1
	mov	r0, #0x1000000
    1:  subs	r0,r0,#1
	bne	1b
#endif

	
	// Move mmu tables into RAM so page table walks by the cpu
	// don't interfere with FLASH programming.
	ldr	r0,=mmu_table
	mov     r4, r0
	add     r2, r0, #0x4800     	// End of tables
	mov		r1, #RAM_BASE
	orr		r1, r1, #0x4000			// RAM tables
	mov     r5, r1


	// first, fixup physical address to second level
	// table used to map first 1MB of flash.
	ldr		r3, [r0], #4
	sub		r3, r3, r4
	add		r3, r3, r5
	str		r3, [r1], #4
	// everything else can go as-is
1:
	ldr		r3, [r0], #4
	str		r3, [r1], #4
	cmp		r0, r2
	bne	1b

	//we can add leds here to help debug

	// go back and fixup physical address to second level
	// table used to map first 1MB of SDRAM.
	add     r1, r5, #(0xA00 * 4)
	ldr		r0, [r1]    		// entry for first 1MB of DRAM
	sub     r0, r0, r4
	add		r0, r0, r5
	str		r0, [r1]    		// store it back

	// Flush the cache
	mov		r0, #DCACHE_FLUSH_AREA	/* cache flush region */
	add		r1, r0, #0x8000		/* 32KB cache         */
667:
	mcr    p15,0,r0,c7,c2,5		/* allocate a line    */
	add    r0, r0, #32       	/* 32 bytes/line      */
	teq    r1, r0
	bne    667b
	mcr    p15,0,r0,c7,c6,0		/* invalidate data cache */
        /*CPWAIT  r0*/
	mrc    p15,0,r1,c2,c0,0		/* arbitrary read   */
	mov    r1,r1
	sub    pc,pc,#4
	mcr    p15,0,r0,c7,c10,4
        /*CPWAIT  r0*/
	mrc    p15,0,r1,c2,c0,0		/* arbitrary read   */
	mov    r1,r1
	sub    pc,pc,#4
	nop

	// Set the TTB register to DRAM mmu_table
	mov	r0, r5
	mov	r1, #0
	mcr	p15, 0, r1, c7, c5, 0		// flush I cache
	mcr	p15, 0, r1, c7, c10, 4		// drain WB
	mcr	p15, 0, r0, c2, c0, 0		// load page table pointer
	mcr	p15, 0, r1, c8, c7, 0		// flush TLBs
	CPWAIT  r0


	//Disable software and data breakpoints
	mov	r0,#0
	mcr	p15,0,r0,c14,c8,0  // ibcr0
	mcr	p15,0,r0,c14,c9,0  // ibcr1
	mcr	p15,0,r0,c14,c4,0  // dbcon

	//Enable all debug functionality
	mov	r0,#0x80000000
	mcr	p14,0,r0,c10,c0,0  // dcsr

//we can add leds blink here to help debug
	
	.endm    // _platform_setup1                                      



/*---------------------------------------------------------------------------*/
/* end of hal_platform_setup.h                                               */
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */