hal_platform_setup.h

Intel XScale PXA255 引导Linux的Redboot 版bootloader源代码！

	// Virtual address 0 (Flash boot code).
	// Map 4k page at 0x00000000 virt --> 0xA0000000 physical
	// This allows us to have a writable vector table.
	//   Read-Write, cacheable, bufferable
	SL_XSMPAGE_ENTRY 0xa0000,1,3,1,1

	// Virtual address 0x1000
	// Map 1-to-1, but don't cache or buffer
	//   Read-Write, non-cacheable, non-bufferable         
	.set	__base,1		   
	SL_SMPAGE_ENTRY __base,3,3,3,3,0,0
	.set	__base,__base+1

	// Virtual address 0x2000-0x100000 (remainder of first MEG of flash1)
	// Map 1-to1
	// Read-Write, cacheable, non-bufferable
	.rept	0x100 - 0x2
	SL_SMPAGE_ENTRY __base,3,3,3,3,1,0
	.set	__base,__base+1
	.endr

	// Now is the second level table for the first megabyte
	// of DRAM.
    mmu_table_rambase:
	// Map 4k page at 0xa0000000 virt --> 0x00000000 physical
	// Read-Write, cacheable, non-bufferable
	SL_SMPAGE_ENTRY 0x00000,3,3,3,3,1,0
	.set	__base,__base+1		   

	// Map remainder of first meg of SDRAM
	//   Read-Write, cacheable, non-bufferable
	.set    __base,0xA0001
	.rept	0x100 - 0x1
	SL_XSMPAGE_ENTRY __base,1,3,1,1
	.set	__base,__base+1
	.endr


@ ^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%
@ ^%^%^%^%^%^%^%^%^%   above could be replaced by prememLLI ^%^%^%^%^%^%^%^%^%
@ ^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%^%
_real_platform_setup://Angel SDRAM init code follows

  	//must set the GPIOs up before any chip selects will work

	// GPSRx = 0x00008800 put a 1 on any of the GPIOs (0=unchanged, 1=drive 1)
	ldr		r0,	=GPSRx
	ldr		r1,	=GPSRx_DEFA_VAL
	str		r1, [r0]

	
	//GPSRy = 0xFC000382
	ldr		r0,	=GPSRy
	ldr		r1,	=GPSRy_DEFA_VAL
	str		r1, [r0]

	//GPSRz = 0x0001FFFF
	ldr		r0,	=GPSRz
	ldr		r1,	=GPSRz_DEFA_VAL
	str		r1, [r0]


	//GPCRx = 0x00000000 put a 0 on any of the GPIOs (0=unchanged, 1=drive 0)
	ldr		r0,	=GPCRx
	ldr		r1,	=GPCRx_DEFA_VAL
	str		r1, [r0]
	//GPCRy = 0x00000000
	ldr		r0,	=GPCRy
	ldr		r1,	=GPCRy_DEFA_VAL
	str		r1, [r0]
	//GPCRz = 0x00000000
	ldr		r0,	=GPCRz
	ldr		r1,	=GPCRz_DEFA_VAL
	str		r1, [r0]


	//GPDRx = 0x0000A800 put the GPIOs in the correct direction (0=in, 1=out)
	ldr		r0,	=GPDRx
	ldr		r1,	=GPDRx_DEFA_VAL
	str		r1, [r0]
	//GPDRy = 0xFC000382
	ldr		r0,	=GPDRy
	ldr		r1,	=GPDRy_DEFA_VAL
	str		r1, [r0]
	//GPDRz = 0x0001FFFF
	ldr		r0,	=GPDRz
	ldr		r1,	=GPDRz_DEFA_VAL
	str		r1, [r0]

	//GAFR0x = 0x98400000  setup the alternate functions (00=normal, 01=alt fuct 1, etc)
	ldr		r0,	=GAFR0x
	ldr		r1,	=GAFR0x_DEFA_VAL
	str		r1, [r0]
	//GAFR1x = 0x00000000
	ldr		r0,	=GAFR1x
	ldr		r1,	=GAFR1x_DEFA_VAL
	str		r1, [r0]
	//GAFR0y = 0x000A9558
	ldr		r0,	=GAFR0y
	ldr		r1,	=GAFR0y_DEFA_VAL
	str		r1, [r0]
	//GAFR1y = 0xAAA00000
	ldr		r0,	=GAFR1y
	ldr		r1,	=GAFR1y_DEFA_VAL
	str		r1, [r0]
	//GAFR0z = 0xAAAAAAAA
	ldr		r0,	=GAFR0z
	ldr		r1,	=GAFR0z_DEFA_VAL
	str		r1, [r0]
	//GAFR1z = 0x00000002
	ldr		r0,	=GAFR1z
	ldr		r1,	=GAFR1z_DEFA_VAL
	str		r1, [r0]

	//PSSR = 0x20 clear the RDH and PH bit in the PSSR
	ldr		r0,	=PSSR
	ldr		r1,	=0x30
	str		r1, [r0]

	//init platform

	ldr    r3, =MSC1	
	ldr    r2, =MSC1_VAL	// high - bank 3 Ethernet Controller
	str    r2, [r3]  // need to set MSC1 before trying to write to the HEX LEDs
	ldr    r2, [r3]  // need to read it back to make sure the value latches (see MSC section of manual)


	ldr	r0,   =FPGA_REGS_BASE_PHYSICAL

	mov	r1, #0
	str	r1, [r0, #PCR_OFFSET]

	mov	r1, #0
	str	r1, [r0, #BCR_OFFSET]

	mov	r1, #0
	str	r1, [r0, #BIPR_OFFSET]

	mov	r1, #0
	str	r1, [r0, #BIMR_OFFSET]
  	
	//finish INIT_PLATFORM


  
#if 1
	mov	r0, #0x10000
    1:  subs	r0,r0,#1
	bne	1b
#endif

	//initreset
	ldr   r0, =RCSR
	ldr   r1, [r0]
	mov   r2, #0xF   //RCSR_ALL
	and   r1, r1, r2
	str   r2, [r0]



	
/*
	@********************************************************************            
  @ Initlialize Memory Controller
	@  The sequence below is based on the recommended init steps detailed
	@    in the EAS, chapter 5.
	@

        @ pause for 200 uSecs- allow internal clocks to settle
	@ *Note: only need this if hard reset... doing it anyway for now
	@
*/
//initOST	
	@ ---- Wait 200 usec
	ldr r3, =OSCR_BASE_PHYSICAL    @ reset the OS Timer Count to zero
	mov r2, #0
	str r2, [r3] 
	str r2, [r3]
	str r2, [r3]
	
	ldr r4, =0x300			@ really 0x2E1 is about 200usec, so 0x300 should be plenty
1:	
	ldr r2, [r3] 
	cmp r4, r2
	bgt 1b

	mov r2, #0
	ldr r1, =OSMR0
	str r2, [r1]
	ldr r1, =OSMR1
	str r2, [r1]
	ldr r1, =OSMR2
	str r2, [r1]
	
	ldr r1, =OSMR3
	str r2, [r1]
	ldr r1, =OWER
	str r2, [r1]
	mov r2, #0xF
	ldr r1, =OSSR
	str r2, [r1]

	mov r2, #0x2
	ldr r1, =OIER
	str r2, [r1]
	

	@finish INIT_OST
	
@**************************************************** START ROD CODE ************************


        @ get memory controller base address
        ldr     r1,  =MEMC_BASE_PHYSICAL

@****************************************************************************
@  Step 1
@

        @ write msc0, read back to ensure data latches
        @
        ldr     r2,   =MSC0_VAL
        str     r2,   [r1, #MSC0_OFFSET]
        ldr     r2,   [r1, #MSC0_OFFSET]

        @ write msc1
        ldr     r2,  =MSC1_VAL
        str     r2,  [r1, #MSC1_OFFSET]
        ldr     r2,  [r1, #MSC1_OFFSET]

        @ write msc2
        ldr     r2,  =MSC2_VAL
        str     r2,  [r1, #MSC2_OFFSET]
        ldr     r2,  [r1, #MSC2_OFFSET]

        @ write mecr
        ldr     r2,  =MECR_VAL
        str     r2,  [r1, #MECR_OFFSET]

        @ write mcmem0
        ldr     r2,  =MCMEM0_VAL
        str     r2,  [r1, #MCMEM0_OFFSET]

        @ write mcmem1
        ldr     r2,  =MCMEM1_VAL
        str     r2,  [r1, #MCMEM1_OFFSET]

        @ write mcatt0
        ldr     r2,  =MCATT0_VAL
        str     r2,  [r1, #MCATT0_OFFSET]

        @ write mcatt1
        ldr     r2,  =MCATT1_VAL
        str     r2,  [r1, #MCATT1_OFFSET]

        @ write mcio0
        ldr     r2,  =MCIO0_VAL
        str     r2,  [r1, #MCIO0_OFFSET]

        @ write mcio1
        ldr     r2,  =MCIO1_VAL
        str     r2,  [r1, #MCIO1_OFFSET]

        @ fly-by-dma is defeatured on this part
        @ write flycnfg
        @ldr     r2,  =FLYCNFG_SETTINGS
        @str     r2,  [r1, #FLYCNFG_OFFSET]

        @-------------------------------------------------------
        @ 3rd bullet, Step 1
        @

        @ get the mdrefr settings
        ldr     r3,  =MDREFR_VAL

        @ extract DRI field (we need a valid DRI field)
        @
        ldr     r2,  =0xFFF
        
        @ valid DRI field in r3
        @
        and     r3,  r3,  r2                 
        
        @ get the reset state of MDREFR
        @
        ldr     r4,  [r1, #MDREFR_OFFSET]
        
        @ clear the DRI field
        @
        bic     r4,  r4,  r2
        
        @ insert the valid DRI field loaded above
        @
        orr     r4,  r4,  r3
        
        @ write back mdrefr
        @
        str     r4,  [r1, #MDREFR_OFFSET]

        @ *Note: preserve the mdrefr value in r4 *	

@****************************************************************************
@  Step 2
@

        @ fetch sxcnfg value
        @
        ldr     r2,  =SXCNFG_VAL
        @ write back sxcnfg
        str     r2,  [r1, #SXCNFG_OFFSET]

        @ if sxcnfg=0, don't program for synch-static memory
        @cmp     r2,  #0
        @beq     1f

        @program sxmrs
        @ldr     r2,  =SXMRS_SETTINGS
        @str     r2,  [r1, #SXMRS_OFFSET]


@****************************************************************************
@  Step 3
@

        @ Assumes previous mdrefr value in r4, if not then read current mdrefr

        @ clear the free-running clock bits
        @ (clear K0Free, K1Free, K2Free
        @
        bic     r4,  r4,  #(0x00800000 | 0x01000000 | 0x02000000)
        
        @ set K1RUN if bank 0 installed
        @
        orr   r4,  r4,  #0x00010000

	@added by alvin, clear K1DB2 to set SDRAM_CLK = MEM_CLK
	bic   r4,  r4,  #0x00020000

        @ write back mdrefr
        @
        str     r4,  [r1, #MDREFR_OFFSET]
        ldr     r4,  [r1, #MDREFR_OFFSET]

        @ deassert SLFRSH
        @
        bic     r4,  r4,  #0x00400000
        
        @ write back mdrefr
        @
        str     r4,  [r1, #MDREFR_OFFSET]

        @ assert E1PIN
        @
        orr     r4,  r4,  #0x00008000
        
        @ write back mdrefr
        @
        str     r4,  [r1, #MDREFR_OFFSET]
        ldr     r4,  [r1, #MDREFR_OFFSET]
        nop
        nop


@****************************************************************************
@  Step 4
@

        @ fetch platform value of mdcnfg
        @
        ldr     r2,  =MDCNFG_VAL                       

        @ disable all sdram banks
        @
        bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
        bic     r2,  r2,  #(MDCNFG_DE2 | MDCNFG_DE3)

        @ program banks 0/1 for bus width
        @
        @bic   r2,  r2,  #MDCNFG_DWID0      @0=32-bit


        @ write initial value of mdcnfg, w/o enabling sdram banks
        @
        str     r2,  [r1, #MDCNFG_OFFSET]

@ ****************************************************************************
@  Step 5
@
        
        @ pause for 200 uSecs
        @
    	ldr r3, =OSCR_BASE_PHYSICAL                      @reset the OS Timer Count to zero
    	mov r2, #0 
	str r2, [r3] 
	ldr r4, =0x300			@really 0x2E1 is about 200usec, so 0x300 should be plenty
1:	
	ldr r2, [r3] 
	cmp r4, r2
	bgt 1b
        

@****************************************************************************
@  Step 6
@

	mov    r0, #0x78				    @turn everything off 
	mcr    p15, 0, r0, c1, c0, 0		@(caches off, MMU off, etc.)


@ ****************************************************************************
@  Step 7
@
        @ Access memory *not yet enabled* for CBR refresh cycles (8)
        @ - CBR is generated for all banks
        
	    ldr     r2, =SDRAM_BASE_PHYSICAL
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]
	    str     r2, [r2]


@ ****************************************************************************
@  Step 8: NOP (enable dcache if you wanna... we dont)
@


@ ****************************************************************************
@  Step 9
@


        @get memory controller base address
        @
        ldr     r1,  =MEMC_BASE_PHYSICAL

        @fetch current mdcnfg value
        @
        ldr     r3,  [r1, #MDCNFG_OFFSET]

        @enable sdram bank 0 if installed (must do for any populated bank)
        @
        orr     r3,  r3,  #MDCNFG_DE0

        @write back mdcnfg, enabling the sdram bank(s)
        @
        str     r3,  [r1, #MDCNFG_OFFSET]