hal_platform_setup.h

Intel XScale PXA255 引导Linux的Redboot 版bootloader源代码！

#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
#define CYGONCE_HAL_PLATFORM_SETUP_H

/*=============================================================================
//
//      hal_platform_setup.h
//
//      Platform specific support for HAL (assembly code)
//
//=============================================================================
//####COPYRIGHTBEGIN####
//                                                                          
// -------------------------------------------                              
// The contents of this file are subject to the Red Hat eCos Public License 
// Version 1.1 (the "License")// you may not use this file except in         
// compliance with the License.  You may obtain a copy of the License at    
// http://www.redhat.com/                                                   
//                                                                          
// Software distributed under the License is distributed on an "AS IS"      
// basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.  See the 
// License for the specific language governing rights and limitations under 
// the License.                                                             
//                                                                          
// The Original Code is eCos - Embedded Configurable Operating System,      
// released September 30, 1998.                                             
//                                                                          
// The Initial Developer of the Original Code is Red Hat.                   
// Portions created by Red Hat are                                          
// Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc.                             
// All Rights Reserved.                                                     
// -------------------------------------------                              
//                                                                          
//####COPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    alvin
// Contributors: 
// Date:         2002-08-01
// Purpose:      Intel SITSANG platform specific support routines
// Description: 
// Usage:       #include <cyg/hal/hal_platform_setup.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/

#include <pkgconf/system.h>             // System-wide configuration info
#include CYGBLD_HAL_PLATFORM_H          // Platform specific configuration
#include <cyg/hal/hal_sitsang.h>        // Platform specific hardware definitions
#include <cyg/hal/hal_mmu.h>            // MMU definitions


.set	Mode_SVC,		0x13
.set	Mode_USR,		0x10
.set	NoIntsMask,		0x000000C0
.set	IRQIntsMask,		0x7F   
.set	IrqFiqEnable,		0xFFFFFF3F

.set PERIF_BASE_PHYSICAL,	0x40000000
.set SDRAM_BASE_PHYSICAL,       0xA0000000
.set PERIF_BASE_PHYSICAL,	0x40000000
.set MEMC_BASE_PHYSICAL,        0x48000000

.set CLK_OFFSET,    		0x01300000      @ Clock Manager
.set OST_OFFSET,     		0x00A00000      @ OS Timer
.set INTC_OFFSET,     		0x00D00000      @ Interrupt controller
.set ICMR_OFFSET,		0x4      @Interrupt controller mask register
.set ICLR_OFFSET,		0x8      @Interrupt controller level register
.set CCCR_OFFSET,     		0x0      @Core Clock Configuration Register
.set CKEN_OFFSET,     		0x4      @Clock Enable Register

	
.set INTC_BASE_PHYSICAL,	(PERIF_BASE_PHYSICAL + INTC_OFFSET)
.set CLK_BASE_PHYSICAL,		(PERIF_BASE_PHYSICAL + CLK_OFFSET)


.set GPIOREGS_PHYSICAL_BASE,    0x40E00000
.set ICLR_BASE_PHYSICAL,	(INTC_BASE_PHYSICAL + ICLR_OFFSET)
.set ICMR_BASE_PHYSICAL,	(INTC_BASE_PHYSICAL + ICMR_OFFSET)
.set CKEN_BASE_PHYSICAL,	(CLK_BASE_PHYSICAL + CKEN_OFFSET)
.set CCCR_BASE_PHYSICAL,	(CLK_BASE_PHYSICAL + CCCR_OFFSET)
.set OST_BASE_PHYSICAL,		(PERIF_BASE_PHYSICAL + OST_OFFSET)


.set OSCR_OFFSET, 		0x10	@OS timer counter register
.set OSCR_BASE_PHYSICAL, 	(OST_BASE_PHYSICAL + OSCR_OFFSET)

.set CLK_BASE_PHYSICAL,		(PERIF_BASE_PHYSICAL + CLK_OFFSET)
.set OSCC_OFFSET,		0x8      @Oscillator Configuration Register
.set OSCC_BASE_PHYSICAL,	(CLK_BASE_PHYSICAL + OSCC_OFFSET)
.set OST_BASE_PHYSICAL,     	(PERIF_BASE_PHYSICAL + OST_OFFSET)

.set OSCC_OON,			0x00000002

	
@ /////////////////////////////////////////////////////////////////////////////////////////
@ /* REGISTER-SPECIFIC OFFSETS */
@ /////////////////////////////////////////////////////////////////////////////////////////

@//
@// MEMC
@//
.set MDCNFG_OFFSET,		0x0
.set MDREFR_OFFSET,		0x4
.set MSC0_OFFSET,		0x8
.set MSC1_OFFSET,		0xC
.set MSC2_OFFSET,		0x10
.set MECR_OFFSET,		0x14
.set SXLCR_OFFSET,		0x18
.set SXCNFG_OFFSET,		0x1C
.set FLYCNFG_OFFSET,		0x20
.set SXMRS_OFFSET,		0x24                                       
.set MCMEM0_OFFSET,		0x28
.set MCMEM1_OFFSET,		0x2C
.set MCATT0_OFFSET,		0x30
.set MCATT1_OFFSET,		0x34
.set MCIO0_OFFSET,		0x38
.set MCIO1_OFFSET,		0x3C
.set MDMRS_OFFSET,		0x40
.set BOOT_DEF_OFFSET,		0x44


@ -----------------------------------------------------------------------------
@ --------------- SITSANG   Section ---------------------------------------------
@ -----------------------------------------------------------------------------

@
@ Sitsang: Boot ROM (flash)
@
.set BOOT_FLASH_BASE_PHYSICAL        ,          0x00000000
    
@
@ Sitsang: Application FLASH (32 MB)
@
.set APP_FLASH_BASE_PHYSICAL         ,          0x00100000
    
@
@ Sitsang: Sitsang Registers (FPGA- aka BLR)
@
.set FPGA_REGS_BASE_PHYSICAL         ,          0x08000000
    
@
@Memory banks disable bits
@
.set MDCNFG_DE0, 				0x00000001
.set MDCNFG_DE1,				0x00000002
.set MDCNFG_DE2, 				0x00010000
.set MDCNFG_DE3, 				0x00020000

.set MDCNFG_DWID0, 				0x0000004
.set MDREFR_APD, 				0x00100000

.set MDREFR_E0PIN,      	   		0x00001000
.set MDREFR_E1PIN,         			0x00008000
.set MDREFR_K0DB2,				0x00004000
.set MDREFR_K1DB2,				0x00020000
.set MDREFR_K2DB2,				0x00080000


@
@ SDRAM Settings
.set MDCNFG_VAL  ,    0x00001AC9              @ SDRAM Config Reg 
.set MDREFR_VAL  ,    0x000BC017              @alvin changed, SDCLK=1/2 MEM_CLK
@.set MDREFR_VAL  ,    0x000BC018              @ SDRAM Refresh Reg  SDCLK=1/2 memory clock
.set MDREFR_VAL_100  ,    0x00018018              @ SDRAM Refresh Reg SDCLK=memory clock
.set MDMRS_VAL   ,    0x00000000              @ SDRAM Mode Reg Set Config Reg

@ Static Memory Settings
@
.set MSCO_28f128J3A_PM,   0xFFF924F2
.set MSC0_28f128J3A_NB,   0xFFF92BF0
.set MSC0_VAL     ,    0xFFF924F2  
@.set MSC0_VAL    ,    0x23F223F2              @ Static Mem. Control Reg 0
@.set MSC0_VAL	,	  0x46F246F2				@ changed to solve frequency change problem

.set MSC1_VAL    ,    0x98B1              @ Static Mem. Control Reg 1
@.set MSC1_VAL    ,    0x3FF1C881              @ changed to solve frequency change problem

.set MSC2_VAL    ,    0xFFB9              @ Static Mem. Control Reg 2 - NOT USED

@ PCMCIA and CF Interfaces
@
.set MECR_VAL    ,    0x00000000              @ eXpansion memory (PCMCIA/CF) bus config. reg
.set MCMEM0_VAL  ,    0x00000000              @ Card I-face Common Mem Space socket 0 timing config ?still TBA
.set MCMEM1_VAL  ,    0x00000000              @ Card I-face Common Mem Space socket 1 timing config ?still TBA
.set MCATT0_VAL  ,    0x00000000              @ Card I-face Attribute Space socket 0 timing config  ?still TBA
.set MCATT1_VAL  ,    0x00000000              @ Card I-face Attribute Space socket 1 timing config  ?still TBA
.set MCIO0_VAL   ,    0x00000000              @ Card I-face I/O Space socket 0 timing config        ?still TBA
.set MCIO1_VAL   ,    0x00000000              @ Card I-face I/O Space socket 1 timing config        ?still TBA

@ Synch. Static Memory
@
.set SXCNFG_VAL  ,    0x00000000              @ Synch. Static Mem. Config. Reg.
.set SXMRS_VAL   ,    0x00000000              @ Synch. Static Mem. Mode Register Set Config - NOT USED
.set SXLCR_VAL   ,    0x00000000              @ Synch. Static Mem. Config. Reg. - NOT USED


.set FLYCNFG_VAL ,    0x00000020              @ Fly-by-DMA config. reg - NOT USED


@
@ [** Sitsang: FPGA Register (BLR) offsets from base address **]
@
.set    PCR_OFFSET   ,           0x00
.set    BCR_OFFSET   ,           0x04
.set    BSR_OFFSET   ,           0x08
.set    BIPR_OFFSET  ,           0x0C
.set    BIMR_OFFSET  ,           0x10
.set    AXHR_OFFSET  ,           0x14
.set    AXLR_OFFSET  ,           0x18
.set    AYHR_OFFSET  ,           0x1C
.set    JSSR_OFFSET  ,           0x20
.set    LLEDR_OFFSET  ,          0x24
.set    HLEDR_OFFSET  ,          0x28
.set    EXBCR_OFFSET  ,          0x2C
.set	EXBSR_OFFSET  ,		 0x30
.set    EXBIPR_OFFSET ,          0x34
.set    EXBIMR_OFFSET ,          0x38



@
@ [** FPGA (aka BLR) Initial Settings **]
@
.set BLANKLED_ALL          ,    (0x6000)		@ 


@ Sitsang/Cotulla values for Core Clock Configuration Register
@ used to set the core freq, memclk freq, and sdclk freq
@ val for L, Mem Clk
@.set  CCCR_L09,      (0x1F)      
.set  CCCR_L27,      (0x1)
@.set  CCCR_L32,      (0x2)
.set  CCCR_L36,      (0x3)
@.set  CCCR_L40,      (0x4)
.set  CCCR_L45,      (0x5)

@ field values for M, memory-to-run-mode  multiplier
.set  CCCR_M1 ,      (0x1 << 5)
.set  CCCR_M2 ,      (0x2 << 5)
.set  CCCR_M4 ,      (0x3 << 5)

@ field values for N, run-mode-to-turbo-mode  multiplier
.set  CCCR_N10,      (0x2 << 7)         @ N=1.0
.set  CCCR_N15,      (0x3 << 7)         @ N=1.5
.set  CCCR_N20,      (0x4 << 7)         @ N=2.0
@.set  CCCR_N25,      (0x5 << 7)         @ N=2.5
.set  CCCR_N30,      (0x6 << 7)         @ N=3.0

@clock settings
.set PLATFORM_MEMORY       ,    CCCR_L27
.set CORE_CLK_100MHZ       ,    (PLATFORM_MEMORY | CCCR_M1 |CCCR_N10)
.set CORE_CLK_133MHZ       ,    (CCCR_L36 | CCCR_M1 | CCCR_N10)
.set CORE_CLK_200MHZ       ,    (PLATFORM_MEMORY | CCCR_M2 | CCCR_N10)
.set CORE_CLK_300MHZ       ,    (PLATFORM_MEMORY | CCCR_M2 | CCCR_N15)
.set CORE_CLK_400MHZ       ,    (PLATFORM_MEMORY | CCCR_M2 | CCCR_N20)
.set CORE_CLK_400MHZ_2     ,    (PLATFORM_MEMORY | CCCR_M4 | CCCR_N10)
.set CORE_CLK_DEFAULT      ,    (CORE_CLK_400MHZ_2)
.set CORE_CLK_ALT          ,    (CORE_CLK_100MHZ)
	

@
@  GPIO Defs
@
.set GPDRx_DEFA_VAL        ,    (0x08108000)	@ GPIO Direction
.set GPDRy_DEFA_VAL        ,    (0x00300002)
.set GPDRz_DEFA_VAL        ,    (0x0001C000)

.set GRERx_DEFA_VAL	      ,    (0x00000000)	@ GPIO Rising-Edge Detect
.set GRERy_DEFA_VAL	      ,    (0x00000000)
.set GRERz_DEFA_VAL	      ,    (0x00000000)

.set GFERx_DEFA_VAL	      ,    (0x00000000)	@ GPIO Falling-Edge Detect
.set GFERy_DEFA_VAL	      ,    (0x00000000)
.set GFERz_DEFA_VAL	      ,    (0x00000000)

                                            @ GPIO Alternate Functions
.set GAFR0x_DEFA_VAL       ,    (0x80000000)
.set GAFR1x_DEFA_VAL       ,    (0x80000000)

.set GAFR0y_DEFA_VAL       ,    (0x00000000)
.set GAFR1y_DEFA_VAL       ,    (0x00000A00)

.set GAFR0z_DEFA_VAL       ,    (0xA0000000)
.set GAFR1z_DEFA_VAL       ,    (0x00000002)

.set GPSRx_DEFA_VAL        ,    0x00008000     @ GPIO Set Regs
.set GPSRy_DEFA_VAL        ,    0x00300002
.set GPSRz_DEFA_VAL        ,    0x0001C000

.set GPCRx_DEFA_VAL        ,    0x00000000     @ GPIO Clear Regs
.set GPCRy_DEFA_VAL        ,    0x00000000
.set GPCRz_DEFA_VAL        ,    0x00000000


// Define macro used to diddle the LEDs during early initialization.
// Can use r0+r1.  Argument in \x.

// The main useful output of this file is PLATFORM_SETUP1: it invokes lots
// of other stuff (may depend on RAM or ROM start).  The other stuff is
// divided into further macros to make it easier to manage what's enabled
// when.

#if defined(CYG_HAL_STARTUP_ROM)
#define PLATFORM_SETUP1 _platform_setup1
//#define CYGHWR_HAL_ARM_HAS_MMU
#else
#define PLATFORM_SETUP1
#endif



#define RAM_BASE	0xa0000000
#define	DRAM_SIZE	(64*1024*1024)		// max size of available SDRAM
#define	DCACHE_SIZE	(32*1024)		// size of the Dcache
#define DCACHE_FLUSH_AREA (RAM_BASE+DRAM_SIZE)  // NB: needs page table support

#define MMU_Control_BTB 0x800

// Reserved area for battery backup SDRAM memory test
// This area is not zeroed out by initialization code
#define	SDRAM_BATTERY_TEST_BASE		0xA1FFFFF0	// base address of last 16 memory locations in a 32MB SDRAM

	.macro  getHexSwitch reg1, reg2
		ldr \reg2, =FPGA_REGS_BASE_PHYSICAL
		ldr \reg1, [\reg2, #JSSR_OFFSET]
		mov \reg1, \reg1, LSR #8
		and \reg1, \reg1, #0xf
	.endm
	
	.macro MEM_TEST
		nop	
	.endm

		
	// Trigger the logic analyzer by writing a particular
	// address, and triggering on that address.
	.macro TRIGGER_LA_ON_ADDRESS address, reg0, reg1
	mrc	p15, 0, \reg0, c1, c0, 0     // read ARM control register
	//	CPWAIT  \reg0
	ldr	\reg1, =\address
	str	\reg0, [\reg1]
	.endm

	// Delay a bit
	.macro DELAY_FOR cycles, reg0
	ldr	\reg0, =\cycles
	subs	\reg0, \reg0, #1
	subne	pc,  pc, #0xc
	.endm
	
	// wait for coprocessor write complete
	.macro CPWAIT reg
        mrc  p15,0,\reg,c2,c0,0
	mov  \reg,\reg
	sub  pc,pc,#4
	.endm

	// form a first-level section entry
	.macro FL_SECTION_ENTRY base,x,ap,p,d,c,b
	.word (\base << 20) | (\x << 12) | (\ap << 10) | (\p << 9) |\
	      (\d << 5) | (\c << 3) | (\b << 2) | 2
	.endm

	// form a first-level page table entry
	.macro FL_PT_ENTRY base,d
	// I wanted to use logical operations here, but since I am using symbols later 
	// to fill in the parameters, I had to use addition to force the assembler to
	// do it right
	.word \base + (\d << 5) + 1
	.endm

	// form a second level small page entry
	.macro SL_SMPAGE_ENTRY base,ap3,ap2,ap1,ap0,c,b
	.word (\base << 12) | (\ap3 << 10) | (\ap2 << 8) | (\ap1 << 6) |\
	      (\ap0 << 4) | (\c << 3) | (\b << 2) | 2
	.endm

	// form a second level extended small page entry
	.macro SL_XSMPAGE_ENTRY base,x,ap,c,b
	.word (\base << 12) | (\x << 6) | (\ap << 4) | (\c << 3) | (\b << 2) | 3
	.endm


	// start of platform setup
	.macro _platform_setup1

	// This is where we wind up immediately after reset. On the CYCLONE, we have
	// to jump around a hole in flash which runs from 0x00001000 - 0x0001fff.  We might not have to do this for sitsang
	// The start of _platform_setup1 will be below 0x1000 and since we need to
	// align the mmu table on a 16k boundary, we just branch around the page
	// table which we will locate at FLASH_BASE+0x4000.
	b _real_platform_setup

	.p2align 13
	// the following alignment creates the mmu table at address 0x4000.
    mmu_table:

	// 1MB of FLASH with i80312 MMRs mapped in using 4K small pages so we can
	// set the access permission on flash and memory-mapped registers properly.
	FL_PT_ENTRY mmu_table_flashbase,0

	// Remaining 63MB of FLASH
	//   rw, cacheable, non-bufferable
	.set	__base,1
	.rept	0x040-0x001
	FL_SECTION_ENTRY __base,0,3,0,0,1,0
	.set	__base,__base+1
	.endr	

	// nothing interesting here (Address Translation)
	.rept	0xA00 - 0x40
	FL_SECTION_ENTRY __base,0,3,0,0,0,0
	.set	__base,__base+1
	.endr

	// up to 64MB SDRAM
	//   x=c=b=1
	// first 1MB mapped by second level table
	FL_PT_ENTRY mmu_table_rambase,0
	.set	__base,__base+1
	
	// remainder of SDRAM mapped 1-to-1
	.rept	0xA20 - 0xA01
	FL_SECTION_ENTRY __base,0,3,0,0,1,0
	.set	__base,__base+1
	.endr

	// Cache flush region.
	// Don't need physical memory, just a cached area.
	.rept	0xD00 - 0xA20
	FL_SECTION_ENTRY __base,0,3,0,0,1,0
	.set	__base,__base+1
	.endr
	
	// Invalid
	.rept	0x1000 - 0xD00
	.word 0
	.set	__base,__base+1
	.endr

	// only I/O at 0xFE8xxxxx
//	.rept	0x1000 - 0xF00
//	FL_SECTION_ENTRY __base,0,3,0,0,0,0
//	.set	__base,__base+1
//	.endr

	// Immediately after the above table (at 0x8000) is the
	// second level page table which breaks up the lowest 1MB
	// of physical memory into 4KB sized virtual pages.
    mmu_table_flashbase: