📄 vectors.s
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// #========================================================================// #// # vectors.S// #// # ARM exception vectors// #// #========================================================================// ####COPYRIGHTBEGIN####// // ------------------------------------------- // The contents of this file are subject to the Red Hat eCos Public License // Version 1.1 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://www.redhat.com/ // // Software distributed under the License is distributed on an "AS IS" // basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See the // License for the specific language governing rights and limitations under // the License. // // The Original Code is eCos - Embedded Configurable Operating System, // released September 30, 1998. // // The Initial Developer of the Original Code is Red Hat. // Portions created by Red Hat are // Copyright (C) 1998, 1999, 2000, 2001 Red Hat, Inc. // All Rights Reserved. // ------------------------------------------- // // ####COPYRIGHTEND####// #========================================================================// ######DESCRIPTIONBEGIN####// #// # Author(s): nickg, gthomas// # Contributors: nickg, gthomas// # Date: 1999-02-20// # Purpose: ARM exception vectors// # Description: This file defines the code placed into the exception// # vectors. It also contains the first level default VSRs// # that save and restore state for both exceptions and// # interrupts.// #// #####DESCRIPTIONEND####// #// #========================================================================#include <pkgconf/hal.h>#include <pkgconf/hal_arm.h>#ifdef CYGPKG_KERNEL // no CDL yet#include <pkgconf/kernel.h>#else# undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT# undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK#endif#include <cyg/hal/hal_platform_setup.h>#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS// The CDL should enforce this#undef CYGHWR_HAL_ARM_DUMP_EXCEPTIONS#endif#include "arm.inc"#ifdef __thumb__// Switch to thumb mode#define THUMB_MODE(_r_, _l_) \ ldr _r_,=_l_ ## f+1 ;\ bx _r_ ;\ .pool ;\ .code 16 ;\ .thumb_func ;\ _l_:// Switch to ARM mode#define ARM_MODE(_r_, _l_) \ ldr _r_,=_l_ ## f ;\ bx _r_ ;\ .pool ;\ .code 32 ;\ _l_:// Function definition, start executing body in ARM mode#define FUNC_START_ARM(_name_, _r_) \ .code 16 ;\ .thumb_func ;\ .globl _name_ ;\_name_: ;\ ldr _r_,=_name_ ## _ARM ;\ bx _r_ ;\ .code 32 ;\_name_ ## _ARM:#else// Switch to thumb mode#define THUMB_MODE(_r_, _l_)// Switch to ARM mode#define ARM_MODE(_r_, _l_)// Function definition, start executing body in ARM mode#define FUNC_START_ARM(_name_, _r_) \ .globl _name_; \_name_: #endif #define PTR(name) \.##name: .word name#ifdef CYGHWR_HAL_ARM_HAS_MMU#define UNMAPPED(x) ((x)-__exception_handlers)#else#define UNMAPPED(x) (x)#endif #define UNMAPPED_PTR(name) \.##name: .word UNMAPPED(name) .file "vectors.S"// CYGHWR_LED_MACRO can be defined in hal_platform_setup.h. It's free to// use r0+r1. Argument is in "\x" - cannot use macro arguments since the// macro may contain #-chars and use of arguments cause these to be // interpreted as CPP stringify operators.// See example in PID hal_platform_setup.h.#ifndef CYGHWR_LED_MACRO#define CYGHWR_LED_MACRO#endif .macro LED x CYGHWR_LED_MACRO.endm//==========================================================================// Hardware exception vectors.// This entire section will be copied to location 0x0000 at startup time.// .code 32 .section ".vectors","ax" .global __exception_handlers__exception_handlers: ldr pc,.reset_vector // 0x00 ldr pc,.undefined_instruction // 0x04 ldr pc,.software_interrupt // 0x08 start && software int ldr pc,.abort_prefetch // 0x0C ldr pc,.abort_data // 0x10 .word 0 // unused ldr pc,.IRQ // 0x18 ldr pc,.FIQ // 0x1C// The layout of these pointers should match the vector table above since// they are copied in pairs. .global vectorsvectors:UNMAPPED_PTR(reset_vector) // 0x20PTR(undefined_instruction) // 0x24PTR(software_interrupt) // 0x28PTR(abort_prefetch) // 0x2CPTR(abort_data) // 0x30 .word 0 // 0x34PTR(IRQ) // 0x38PTR(FIQ) // 0x3cPTR(start) // This is copied to 0x28 for bootup // 0x40 // location 0x40 is used for storing DRAM size if known // for some platforms. //// "Vectors" - fixed location data items// This section contains any data which might be shared between// an eCos application and any other environment, e.g. the debug// ROM. // .section ".fixed_vectors" // Interrupt/exception VSR pointers .globl hal_vsr_tablehal_vsr_table: .rept 8 .long 0 .endr .globl hal_dram_sizehal_dram_size: .long 0 .balign 16#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT // Vectors used to communicate between eCos and ROM environments .globl hal_virtual_vector_tablehal_virtual_vector_table: .rept CYGNUM_CALL_IF_TABLE_SIZE .long 0 .endr#endif #ifdef CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT .balign 16 // Should be at 0x50ice_thread_vector: .long 0 // Must be 'MICE' .long 0 // Pointer to thread support vector .long 0 // eCos executing flag .long 0 // Must be 'GDB '#endif // CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT .balign 32 // Other vectors - this may include "fixed" locations#ifdef PLATFORM_VECTORS PLATFORM_VECTORS#endif .text // Startup code which will get the machine into supervisor mode .global reset_vector .type reset_vector,functionreset_vector: PLATFORM_SETUP1 // Early stage platform initialization // see <cyg/hal/hal_platform_setup.h> // Come here to reset board .global warm_resetwarm_reset: #if defined(CYG_HAL_STARTUP_RAM) && \ !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) mrs r7,cpsr // move back to IRQ mode and r7,r7,#CPSR_MODE_BITS cmp r7,#CPSR_SUPERVISOR_MODE beq start#endif // We cannot access any LED registers until after PLATFORM_SETUP1 LED 7 mov r0,#0 // move vectors // We cannot perform a store until after PLATFORM_SETUP1 // Some boards initialize this elsewhere.#if !defined(CYGPKG_HAL_ARM_EBSA285) && \ !defined(CYGPKG_HAL_ARM_SA11X0) && \ !defined(CYGPKG_HAL_ARM_IQ80310) ldr r1,=hal_dram_size str r0, [r1] // DRAM size to zero => unknown#endif ldr r1,=__exception_handlers#ifndef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS // Wait with this if stubs are included (see further down). ldr r2,[r1,#0x04] // undefined instruction str r2,[r0,#0x04] ldr r2,[r1,#0x24] str r2,[r0,#0x24]#endif ldr r2,[r1,#0x08] // software interrupt str r2,[r0,#0x08]#ifdef CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT ldr r2,=ice_thread_vector sub r2,r2,r1 // compute fixed (low memory) address ldr r3,=0x4D494345 // 'MICE' str r3,[r2],#4 ldr r3,=hal_arm_ice_thread_handler str r3,[r2],#4 mov r3,#1 str r3,[r2],#4 ldr r3,=0x47444220 // 'GDB ' str r3,[r2],#4#endif // CYGHWR_HAL_ARM_ICE_THREAD_SUPPORT#if defined(CYG_HAL_STARTUP_RAM)// Ugly hack to get into supervisor mode ldr r2,[r1,#0x40] str r2,[r0,#0x28] LED 6 swi // switch to supervisor mode#endif // =========================================================================// Real startup code. We jump here from the reset vector to set up the world. .globl startstart: LED 5#if defined(CYG_HAL_STARTUP_RAM) && \ !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)// If we get restarted, hang here to avoid corrupting memory ldr r0,.init_flag ldr r1,[r0]1: cmp r1,#0 bne 1b ldr r1,init_done str r1,[r0]#endif // Reset software interrupt pointer mov r0,#0 // move vectors ldr r1,.__exception_handlers#if defined(CYG_HAL_STARTUP_RAM) && \ !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) cmp r7,#CPSR_SUPERVISOR_MODE beq 10f#endif ldr r2,[r1,#0x28] // software interrupt str r2,[r0,#0x28]10: ldr r2,[r1,#0x18] // IRQ str r2,[r0,#0x18] ldr r2,[r1,#0x38] str r2,[r0,#0x38] ldr r2,[r1,#0x1C] // FIQ str r2,[r0,#0x1C] ldr r2,[r1,#0x3C] str r2,[r0,#0x3C] ldr r2,[r1,#0x0C] // abort (prefetch) str r2,[r0,#0x0C] ldr r2,[r1,#0x2C] str r2,[r0,#0x2C] ldr r2,[r1,#0x10] // abort (data) str r2,[r0,#0x10] ldr r2,[r1,#0x30] str r2,[r0,#0x30] LED 4#if defined(CYG_HAL_STARTUP_ROM) // Set up reset vector mov r0,#0 ldr r1,.__exception_handlers ldr r2,[r1,#0x00] // reset vector intstruction str r2,[r0,#0x00] ldr r2,=warm_reset str r2,[r0,#0x20] // Relocate [copy] data from ROM to RAM ldr r3,.__rom_data_start ldr r4,.__ram_data_start ldr r5,.__ram_data_end cmp r4,r5 // jump if no data to move beq 2f sub r3,r3,#4 // loop adjustments sub r4,r4,#41: ldr r0,[r3,#4]! // copy info str r0,[r4,#4]! cmp r4,r5 bne 1b2:#endif // initialize interrupt/exception environments ldr sp,.__startup_stack mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_IRQ_MODE) msr cpsr,r0 ldr sp,.__exception_stack mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_UNDEF_MODE) msr cpsr,r0 ldr sp,.__exception_stack // initialize CPSR (machine state register) mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE) msr cpsr,r0 // Note: some functions in LIBGCC1 will cause a "restore from SPSR"!!
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