📄 lan91c96.h
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*/#define LAN91C96_AUTOTX (0xFFU << 0)/********************************************************************************* Packet Number Register - Bank 2 - Offset 2********************************************************************************/#define LAN91C96_PNR_TX (0x1FU << 0)/********************************************************************************* Allocation Result Register - Bank 2 - Offset 3********************************************************************************/#define LAN91C96_ARR_ALLOC_PN (0x7FU << 0)#define LAN91C96_ARR_FAILED (0x1U << 7)/********************************************************************************* FIFO Ports Register - Bank 2 - Offset 4********************************************************************************/#define LAN91C96_FIFO_TX_DONE_PN (0x1FU << 0)#define LAN91C96_FIFO_TEMPTY (0x1U << 7)#define LAN91C96_FIFO_RX_DONE_PN (0x1FU << 8)#define LAN91C96_FIFO_RXEMPTY (0x1U << 15)/********************************************************************************* Pointer Register - Bank 2 - Offset 6********************************************************************************/#define LAN91C96_PTR_LOW (0xFFU << 0)#define LAN91C96_PTR_HIGH (0x7U << 8)#define LAN91C96_PTR_AUTO_TX (0x1U << 11)#define LAN91C96_PTR_ETEN (0x1U << 12)#define LAN91C96_PTR_READ (0x1U << 13)#define LAN91C96_PTR_AUTO_INCR (0x1U << 14)#define LAN91C96_PTR_RCV (0x1U << 15)#define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \ LAN91C96_PTR_AUTO_INCR | \ LAN91C96_PTR_READ)/********************************************************************************* Data Register - Bank 2 - Offset 8********************************************************************************/#define LAN91C96_CONTROL_CRC (0x1U << 4) // CRC bit#define LAN91C96_CONTROL_ODD (0x1U << 5) // ODD bit/********************************************************************************* Interrupt Status Register - Bank 2 - Offset 12********************************************************************************/#define LAN91C96_IST_RCV_INT (0x1U << 0)#define LAN91C96_IST_TX_INT (0x1U << 1)#define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2)#define LAN91C96_IST_ALLOC_INT (0x1U << 3)#define LAN91C96_IST_RX_OVRN_INT (0x1U << 4)#define LAN91C96_IST_EPH_INT (0x1U << 5)#define LAN91C96_IST_ERCV_INT (0x1U << 6)#define LAN91C96_IST_RX_IDLE_INT (0x1U << 7)/********************************************************************************* Interrupt Acknowledge Register - Bank 2 - Offset 12********************************************************************************/#define LAN91C96_ACK_TX_INT (0x1U << 1)#define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2)#define LAN91C96_ACK_RX_OVRN_INT (0x1U << 4)#define LAN91C96_ACK_ERCV_INT (0x1U << 6)/********************************************************************************* Interrupt Mask Register - Bank 2 - Offset 12********************************************************************************/#define LAN91C96_MSK_RCV_INT (0x1U << 0)#define LAN91C96_MSK_TX_INT (0x1U << 1)#define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2)#define LAN91C96_MSK_ALLOC_INT (0x1U << 3)#define LAN91C96_MSK_RX_OVRN_INT (0x1U << 4)#define LAN91C96_MSK_EPH_INT (0x1U << 5)#define LAN91C96_MSK_ERCV_INT (0x1U << 6)#define LAN91C96_MSK_TX_IDLE_INT (0x1U << 7)/********************************************************************************* Bank 3 Register Map in I/O Space********************************************************************************/#define LAN91C96_MULTICAST0 0 // Multicast Table 0#define LAN91C96_MULTICAST1 1 // Multicast Table 1#define LAN91C96_MULTICAST2 2 // Multicast Table 2#define LAN91C96_MULTICAST3 3 // Multicast Table 3#define LAN91C96_MULTICAST4 4 // Multicast Table 4#define LAN91C96_MULTICAST5 5 // Multicast Table 5#define LAN91C96_MULTICAST6 6 // Multicast Table 6#define LAN91C96_MULTICAST7 7 // Multicast Table 7#define LAN91C96_MGMT 8 // Management Interface#define LAN91C96_REVISION 10 // Revision Register#define LAN91C96_ERCV 12 // Early Rcv Register/********************************************************************************* Management Interface - Bank 3 - Offset 8********************************************************************************/#define LAN91C96_MGMT_MDO (0x1U << 0)#define LAN91C96_MGMT_MDI (0x1U << 1)#define LAN91C96_MGMT_MCLK (0x1U << 2)#define LAN91C96_MGMT_MDOE (0x1U << 3)#define LAN91C96_MGMT_LOW_ID (0x3U << 4)#define LAN91C96_MGMT_IOS0 (0x1U << 8)#define LAN91C96_MGMT_IOS1 (0x1U << 9)#define LAN91C96_MGMT_IOS2 (0x1U << 10)#define LAN91C96_MGMT_nXNDEC (0x1U << 11)#define LAN91C96_MGMT_HIGH_ID (0x3U << 12)/********************************************************************************* Revision Register - Bank 3 - Offset 10********************************************************************************/#define LAN91C96_REV_REVID (0xFU << 0)#define LAN91C96_REV_CHIPID (0xFU << 4)/********************************************************************************* Early RCV Register - Bank 3 - Offset 12********************************************************************************/#define LAN91C96_ERCV_THRESHOLD (0x1FU << 0)#define LAN91C96_ERCV_RCV_DISCRD (0x1U << 7)/********************************************************************************* PCMCIA Configuration Registers********************************************************************************/#define LAN91C96_ECOR 0x8000 // Ethernet Configuration Register#define LAN91C96_ECSR 0x8002 // Ethernet Configuration and Status/********************************************************************************* PCMCIA Ethernet Configuration Option Register (ECOR)********************************************************************************/#define LAN91C96_ECOR_ENABLE (0x1U << 0)#define LAN91C96_ECOR_WR_ATTRIB (0x1U << 2)#define LAN91C96_ECOR_LEVEL_REQ (0x1U << 6)#define LAN91C96_ECOR_SRESET (0x1U << 7)/********************************************************************************* PCMCIA Ethernet Configuration and Status Register (ECSR)********************************************************************************/#define LAN91C96_ECSR_INTR (0x1U << 1)#define LAN91C96_ECSR_PWRDWN (0x1U << 2)#define LAN91C96_ECSR_IOIS8 (0x1U << 5)/********************************************************************************* Receive Frame Status Word - See page 38 of the LAN91C96 specification.********************************************************************************/#define LAN91C96_TOO_SHORT (0x1U << 10)#define LAN91C96_TOO_LONG (0x1U << 11)#define LAN91C96_ODD_FRM (0x1U << 12)#define LAN91C96_BAD_CRC (0x1U << 13)#define LAN91C96_BROD_CAST (0x1U << 14)#define LAN91C96_ALGN_ERR (0x1U << 15)#ifdef NO_BROADCAST#define FRAME_FILTER (LAN91C96_TOO_SHORT | \ LAN91C96_TOO_LONG | \ LAN91C96_BAD_CRC | \ LAN91C96_BROD_CAST | \ LAN91C96_ALGN_ERR)#else#define FRAME_FILTER (LAN91C96_TOO_SHORT | \ LAN91C96_TOO_LONG | \ LAN91C96_BAD_CRC | \ LAN91C96_ALGN_ERR)#endif // NO_BROADCAST/********************************************************************************* Default MAC Address********************************************************************************/#define MAC_DEF_HI 0x0800#define MAC_DEF_MED 0x3333#define MAC_DEF_LO 0x0100/********************************************************************************* Default I/O Signature - 0x33********************************************************************************/#define LAN91C96_LOW_SIGNATURE (0x33U << 0)#define LAN91C96_HIGH_SIGNATURE (0x33U << 8)#define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE) /********************************************************************************* Error codes********************************************************************************/#define LAN91C96_NO_ERROR 0 // No error/********************************************************************************* Sub-location codes - 8 bits max - 253 possible sub-location codes.********************************************************************************/#define ERR_LAN91C96_INV_DEV 0x01#define ERR_LAN91C96_BAD_MAC 0x02#define ERR_LAN91C96_EEPROM 0x03#define ERR_LAN91C96_RESET 0x04#define ERR_LAN91C96_ALLOC 0x05#define ERR_LAN91C96_DEALLOC 0x06#define ERR_LAN91C96_TRANSMIT 0x07#define ERR_LAN91C96_RECEIVE 0x08/********************************************************************************* Timeout Definitions********************************************************************************/#define LAN91C96_TIME_DELAY 3000 // Timeout for seconds#define LAN91C96_TO_EEPROM 72000 // Timeout for access the EEPROM#define LAN91C96_TO_ALLOC 200 // Timeout for buffer allocations#define LAN91C96_TO_TRANSMIT 200 // Timeout for transmit/********************************************************************************* Manifest Constants********************************************************************************/#define LAN91C96_MAX_PAGES 6 // Maximum number of 256 pages.#define ETHERNET_MAX_LENGTH 1514// Physical LAN91C96 Address Space#define SITSANG_LAN91C96_IOREG 0x04000000#define SITSANG_LAN91C96_ATTREG 0x04800000#endif /* _lan91c96_h */⌨️ 快捷键说明
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