📄 lan91c96.h
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/********************************************************************************** COPYRIGHT (C) 2000, 2001 Intel Corporation.**** This software as well as the software described in it is furnished under ** license and may only be used or copied in accordance with the terms of the ** license. The information in this file is furnished for informational use ** only, is subject to change without notice, and should not be construed as ** a commitment by Intel Corporation. Intel Corporation assumes no ** responsibility or liability for any errors or inaccuracies that may appear ** in this document or any software that may be provided in association with ** this document. ** Except as permitted by such license, no part of this document may be ** reproduced, stored in a retrieval system, or transmitted in any form or by ** any means without the express written consent of Intel Corporation. **** FILENAME: lan91c96.h**** PURPOSE: This is the main header file for the LAN91C96 Ethernet** Controller.**** LAST MODIFIED: $Modtime: 9/25/01 2:12p $******************************************************************************/#ifndef _lan91c96_h#define _lan91c96_h/********************************************************************************* HEADER FILES********************************************************************************///#include "lan91c96API.h" // Include all dependent header files needed/********************************************************************************* Bank Select Field********************************************************************************/#define LAN91C96_BANK_SELECT 14 // Bank Select Register#define LAN91C96_BANKSELECT (0x3UC << 0)#define BANK0 0x00#define BANK1 0x01#define BANK2 0x02#define BANK3 0x03#define BANK4 0x04/********************************************************************************* EEPROM Addresses.********************************************************************************/#define EEPROM_MAC_OFFSET_1 0x6020#define EEPROM_MAC_OFFSET_2 0x6021#define EEPROM_MAC_OFFSET_3 0x6022/********************************************************************************* Bank 0 Register Map in I/O Space********************************************************************************/#define LAN91C96_TCR 0 // Transmit Control Register#define LAN91C96_EPH_STATUS 2 // EPH Status Register#define LAN91C96_RCR 4 // Receive Control Register#define LAN91C96_COUNTER 6 // Counter Register#define LAN91C96_MIR 8 // Memory Information Register#define LAN91C96_MCR 10 // Memory Configuration Register/********************************************************************************* Transmit Control Register - Bank 0 - Offset 0********************************************************************************/#define LAN91C96_TCR_TXENA (0x1U << 0)#define LAN91C96_TCR_LOOP (0x1U << 1)#define LAN91C96_TCR_FORCOL (0x1U << 2)#define LAN91C96_TCR_TXP_EN (0x1U << 3)#define LAN91C96_TCR_PAD_EN (0x1U << 7)#define LAN91C96_TCR_NOCRC (0x1U << 8)#define LAN91C96_TCR_MON_CSN (0x1U << 10)#define LAN91C96_TCR_FDUPLX (0x1U << 11)#define LAN91C96_TCR_STP_SQET (0x1U << 12)#define LAN91C96_TCR_EPH_LOOP (0x1U << 13)#define LAN91C96_TCR_ETEN_TYPE (0x1U << 14)#define LAN91C96_TCR_FDSE (0x1U << 15)/********************************************************************************* EPH Status Register - Bank 0 - Offset 2********************************************************************************/#define LAN91C96_EPHSR_TX_SUC (0x1U << 0)#define LAN91C96_EPHSR_SNGL_COL (0x1U << 1)#define LAN91C96_EPHSR_MUL_COL (0x1U << 2)#define LAN91C96_EPHSR_LTX_MULT (0x1U << 3)#define LAN91C96_EPHSR_16COL (0x1U << 4)#define LAN91C96_EPHSR_SQET (0x1U << 5)#define LAN91C96_EPHSR_LTX_BRD (0x1U << 6)#define LAN91C96_EPHSR_TX_DEFR (0x1U << 7)#define LAN91C96_EPHSR_WAKEUP (0x1U << 8)#define LAN91C96_EPHSR_LATCOL (0x1U << 9)#define LAN91C96_EPHSR_LOST_CARR (0x1U << 10)#define LAN91C96_EPHSR_EXC_DEF (0x1U << 11)#define LAN91C96_EPHSR_CTR_ROL (0x1U << 12)#define LAN91C96_EPHSR_LINK_OK (0x1U << 14)#define LAN91C96_EPHSR_TX_UNRN (0x1U << 15)#define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \ LAN91C96_EPHSR_MUL_COL | \ LAN91C96_EPHSR_16COL | \ LAN91C96_EPHSR_SQET | \ LAN91C96_EPHSR_TX_DEFR | \ LAN91C96_EPHSR_LATCOL | \ LAN91C96_EPHSR_LOST_CARR | \ LAN91C96_EPHSR_EXC_DEF | \ LAN91C96_EPHSR_LINK_OK | \ LAN91C96_EPHSR_TX_UNRN)/********************************************************************************* Receive Control Register - Bank 0 - Offset 4********************************************************************************/#define LAN91C96_RCR_RX_ABORT (0x1U << 0)#define LAN91C96_RCR_PRMS (0x1U << 1)#define LAN91C96_RCR_ALMUL (0x1U << 2)#define LAN91C96_RCR_RXEN (0x1U << 8)#define LAN91C96_RCR_STRIP_CRC (0x1U << 9)#define LAN91C96_RCR_FILT_CAR (0x1U << 14)#define LAN91C96_RCR_SOFT_RST (0x1U << 15)/********************************************************************************* Counter Register - Bank 0 - Offset 6********************************************************************************/#define LAN91C96_ECR_SNGL_COL (0xFU << 0)#define LAN91C96_ECR_MULT_COL (0xFU << 5)#define LAN91C96_ECR_DEF_TX (0xFU << 8)#define LAN91C96_ECR_EXC_DEF_TX (0xFU << 12)/********************************************************************************* Memory Information Register - Bank 0 - OFfset 8********************************************************************************/#define LAN91C96_MIR_SIZE (0x18 << 0) // 6144 bytes/********************************************************************************* Memory Configuration Register - Bank 0 - Offset 10********************************************************************************/#define LAN91C96_MCR_MEM_RES (0xFFU << 0)#define LAN91C96_MCR_MEM_MULT (0x3U << 9)#define LAN91C96_MCR_HIGH_ID (0x3U << 12)#define LAN91C96_MCR_TRANSMIT_PAGES 0x6/********************************************************************************* Bank 1 Register Map in I/O Space********************************************************************************/#define LAN91C96_CONFIG 0 // Configuration Register#define LAN91C96_BASE 2 // Base Address Register#define LAN91C96_IA0 4 // Individual Address Register - 0#define LAN91C96_IA1 5 // Individual Address Register - 1#define LAN91C96_IA2 6 // Individual Address Register - 2#define LAN91C96_IA3 7 // Individual Address Register - 3#define LAN91C96_IA4 8 // Individual Address Register - 4#define LAN91C96_IA5 9 // Individual Address Register - 5#define LAN91C96_GEN_PURPOSE 10 // General Address Registers#define LAN91C96_CONTROL 12 // Control Register/********************************************************************************* Configuration Register - Bank 1 - Offset 0********************************************************************************/#define LAN91C96_CR_INT_SEL0 (0x1U << 1)#define LAN91C96_CR_INT_SEL1 (0x1U << 2)#define LAN91C96_CR_RES (0x3U << 3)#define LAN91C96_CR_DIS_LINK (0x1U << 6)#define LAN91C96_CR_16BIT (0x1U << 7)#define LAN91C96_CR_AUI_SELECT (0x1U << 8)#define LAN91C96_CR_SET_SQLCH (0x1U << 9)#define LAN91C96_CR_FULL_STEP (0x1U << 10)#define LAN91C96_CR_NO_WAIT (0x1U << 12)/********************************************************************************* Base Address Register - Bank 1 - Offset 2********************************************************************************/#define LAN91C96_BAR_RA_BITS (0x27U << 0)#define LAN91C96_BAR_ROM_SIZE (0x1U << 6)#define LAN91C96_BAR_A_BITS (0xFFU << 8)/********************************************************************************* Control Register - Bank 1 - Offset 12********************************************************************************/#define LAN91C96_CTR_STORE (0x1U << 0)#define LAN91C96_CTR_RELOAD (0x1U << 1)#define LAN91C96_CTR_EEPROM (0x1U << 2)#define LAN91C96_CTR_TE_ENABLE (0x1U << 5)#define LAN91C96_CTR_CR_ENABLE (0x1U << 6)#define LAN91C96_CTR_LE_ENABLE (0x1U << 7)#define LAN91C96_CTR_BIT_8 (0x1U << 8)#define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11)#define LAN91C96_CTR_WAKEUP_EN (0x1U << 12)#define LAN91C96_CTR_PWRDN (0x1U << 13)#define LAN91C96_CTR_RCV_BAD (0x1U << 14)/********************************************************************************* Bank 2 Register Map in I/O Space********************************************************************************/#define LAN91C96_MMU 0 // MMU Command Register#define LAN91C96_AUTO_TX_START 1 // Auto Tx Start Register#define LAN91C96_PNR 2 // Packet Number Register#define LAN91C96_ARR 3 // Allocation Result Register#define LAN91C96_FIFO 4 // FIFO Ports Register#define LAN91C96_POINTER 6 // Pointer Register#define LAN91C96_DATA_HIGH 8 // Data High Register #define LAN91C96_DATA_LOW 10 // Data Low Register#define LAN91C96_INT_STATS 12 // Interrupt Status Register - RO#define LAN91C96_INT_ACK 12 // Interrupt Acknowledge Register -WO#define LAN91C96_INT_MASK 13 // Interrupt Mask Register/********************************************************************************* MMU Command Register - Bank 2 - Offset 0********************************************************************************/#define LAN91C96_MMUCR_NO_BUSY (0x1U << 0)#define LAN91C96_MMUCR_N1 (0x1U << 1)#define LAN91C96_MMUCR_N2 (0x1U << 2)#define LAN91C96_MMUCR_COMMAND (0xFU << 4)#define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) // WXYZ = 0010#define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) // WXYZ = 0100#define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) // WXYZ = 0110#define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) // WXYZ = 0111#define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) // WXYZ = 1000#define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) // WXYZ = 1010#define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) // WXYZ = 1100#define LAN91C96_MMUCR_RESET_TX (0xEU << 4) // WXYZ = 1110/********************************************************************************* Auto Tx Start Register - Bank 2 - Offset 1*******************************************************************************⌨️ 快捷键说明
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