📄 dff.vhd
字号:
102
-- Author: Elliot Hill
--
-- Description: This module represents the VHDL equivalent of
-- a T flip flop; One that toggles with every clock
-- pulse, if the T input is active.
--
-- Last Modified: 25 September 2001
--
library ieee;
use ieee.std_logic_1164.all;
entity TFF is
port (T,clk,reset: in BIT;
Q: out BIT);
end;
architecture TFF of TFF is
signal D : BIT := '0';
begin
process (clk,reset)
begin
if (reset = '1') then
D <= '0';
elsif (clk = '1' and not clk'STABLE) then
if (T = '1') then
D <= not D;
end if;
end if;
Q <= D;
end process;
end TFF;
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