reg.vhd

利用Ti公司的TMSvc320c6711开发板的基础上搭建的移动视频电话系统。程序中主要实现3个功能：实时捕捉视频和音频数据；能够对视频和音频数据进行解码和存储；能够通过GPRS通信口传输音/视频压缩

-- Author: Elliot Hill
--
-- Description: This file is used in the MVP (Mobile VideoPhone)
-- thesis to model a set of flip-flops, used for
-- data latching in conjunction with the synctime
-- module. This module takes in the primary and
-- secondary clocks from the synctime module, and
-- latches data coming in from the TVP5040 to the
-- D flip flops.
--
-- Last Modified: 24 September 2001
--
library ieee;
use ieee.std_logic_1164.all;
entity myreg is
port (YIN, UVIN: in STD_LOGIC_VECTOR(0 to 7);
primclk, secclk: in STD_LOGIC;
Y1OUT,Y2OUT,UOUT,VOUT: out STD_LOGIC_VECTOR(0 to 7));
end;
architecture myreg_struct of myreg is
-- A mainly structural design, we need to tell the
-- CPLD that there will be six sets of octal
-- flipflops used.
component DFF8
port (D: in STD_LOGIC_VECTOR(0 to 7);
clk: in STD_LOGIC;
Q: out STD_LOGIC_VECTOR(0 to 7));
end component;
signal Ycap: STD_LOGIC_VECTOR(0 to 7);
signal UVcap: STD_LOGIC_VECTOR(0 to 7);
begin
-- The Yprim and UVprim registers are used to latch
-- the Y1 and V data on primclk, and these are then
-- passed to the second set of registers on secclk.
-- Also on secclk, the Y2 and V data is clocked onto
-- a different pair of registers.
Yprim: DFF8 port map (YIN,primclk,Ycap);
UVprim: DFF8 port map (UVIN,primclk,UVcap);
Y1reg: DFF8 port map (Ycap,secclk,Y1OUT);
Y2reg: DFF8 port map (YIN,secclk,Y1OUT);
Ureg: DFF8 port map (UVcap,secclk,UOUT);
Vreg: DFF8 port map (UVIN,secclk,VOUT);
end myreg_struct;